High Performance DMA Controller
UG0331 User Guide Revision 15.0 258
8.4.1.16 Descriptor 2 Status Register
3 HPDMASR_DCP_DERR[1] 0 Descriptor 1 destination transfer error.
1: Descriptor 1 transfer error
0: No error at destination end during descriptor 1 transfer
This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[1]
of the descriptor 1 Interrupt Clear register.
31:4 Reserved 0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Table 165 • HPDMAD2SR_REG
Bit
Number Name
Reset
Value Description
0 HPDMASR_DCP_ACTIVE[2] 0 Descriptor 2 Transfer in progress.
1: Descriptor 2 transfer in progress.
0: Descriptor 2 is in queue when HPDMACR_DCP_VALID[2]
bit is set in descriptor 2 Control register.
1 HPDMASR_DCP_CMPLET[2] 0 Descriptor 2 transfer complete.
1: Descriptor 2 transfer completed successfully.
0: Descriptor 2 transfer not completed.
This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[2]
of the descriptor 2 Control register.
2 HPDMASR_DCP_SERR[2] 0 Descriptor 2 source transfer error.
1: Descriptor 2 transfer error occurred at source end
0: No error at source end during descriptor 2 transfer
This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[2]
of the descriptor 2 Interrupt Clear register.
3 HPDMASR_DCP_DERR[2] 0 Descriptor 2 destination transfer error.
1: Descriptor 2 transfer error
0: No error at destination end during descriptor 2 transfer
This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[2]
of the descriptor 2 Interrupt Clear register.
31:4 Reserved 0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Table 164 • HPDMAD1SR_REG (continued)
Bit
Number Name
Reset
Value Description
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