Revision History
UG0331 User Guide Revision 15.0 2
• Added clocking information to SGMII Module, page 377 (SAR 75342).
• Added information regarding full behavioral simulation model in the applicable chapters (SAR
80669).
• Removed note from Peripheral Signals Assignment Table, page 443, and removed “System Clock
Frequency” section (SAR 53174).
• Added Power-Up to Functional Time Data, page 646 (SAR 81600).
• Added Error Detection and Correction Controllers, page 792 (SAR 80945).
• Updated Figure 153, page 375, Figure 155, page 380, Figure 160, page 387, and Figure 161,
page 388 (SAR 81447).
• Added a note for Functional Description, page 7 in Cortex-M3 Processor Overview and Debug
Features, page 6 (SAR 81261).
• Updated Table 640, page 639 and Table 641, page 640 (SAR 82053).
• Updated Bit number 2 description in Table 693, page 704 (SAR 82131).
1.5 Revision 11.0
The following changes were made in revision 11.0 of this document.
• Updated Table 367, page 413 and Table 368, page 413 (SAR 58939).
• Updated Locked Transactions, page 231 (SAR 64773).
1.6 Revision 10.0
The following changes were made in revision 10.0 of this document.
• Updated Power-Up to Functional Time Sequence, page 645 (SAR 72958).
• Updated Table 481, page 497 (SAR 70358).
• Updated Functional Description, page 146 chapter in Embedded NVM (eNVM) Controllers,
page 145 chapter (SAR 73736).
• Updated Table 741, page 725 and Ta b le 11 0, page 180 (SAR 70182).
• Added Figure 82, page 160, Figure 83, page 160, Figure 84, page 161, and Figure 86, page 162,
and added eNVM Pages for Special Purpose Storage, page 163 (SAR 66208).
• Updated SPI Use Models, page 525 (SAR 62152).
• Updated Table 104, page 175, Ta b le 11 2, page 180, and Ta ble 6 56, page 684 (SAR 71776).
1.7 Revision 9.0
The following changes were made in revision 9.0 of this document.
• Updated Reset Controller, page 642 (SAR 51042, 65634, 66764, 66981).
• Updated Figure 296, page 661 (SAR 67010)
• Added a note to System Reset, page 654 (SAR 64029)
• Updated FIC Implementation Considerations, page 766 (SAR 64802).
1.8 Revision 8.0
The following changes were made in revision 8.0 of this document.
• Removed M2S100 devices list from Features, page 145, Table 93, page 146, Table 94, page 147,
and Table 114, page 185 (SAR 62858).
• Updated Table 104, page 175 for NV_FREQRNG and replaced FREQRNG with NV_FREQRNG
throughout the document (SAR 62544)
• Updated Page Program, page 152 (SAR 61046).
• Updated System Register Block, page 670 (SAR 62544).
• Added a reference to SmartFusion2 SoC FPGA High Speed DDR Interfaces User Guide in the
HPDMA Use Models, page 245 (SAR 60106).
1.9 Revision 7.0
The following changes were made in revision 3.0 of this document.
• Updated Cache Engine, page 139 (SAR 58874).
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