Error Detection and Correction Controllers
UG0331 User Guide Revision 15.0 793
error, or whether multiple bits are in error, and is useful in systems where it is desirable to keep a log of
which bits have been in error.
When a correctable error is detected (indicated by Err_detect = 1 and Err_multpl = 0), the data bit in error
is corrected as it passes from Data In to Data Out. If the error is not correctable (indicated by Err_multpl
= 1), data passes unchanged from Data In to Data Out.
There are interrupts associated with errors. These are covered in the chapter for each memory type.
26.1.1 EDAC Checksum Bits Width
The following table lists the data width ranges and the corresponding checksum bit widths.
26.2 Configuration
The EDAC architecture is implemented to protect different types of memories. The data and checksum
bit widths of the EDAC change according to the memory specifications.
Refer to the following chapters for EDAC configurations for specific types of memories:
• eSRAM: Embedded SRAM (eSRAM) Controllers
• Internal FIFOs of the Ethernet MAC: Ethernet MAC
• USB internal memory: Universal Serial Bus OTG Controller
• Internal RAM of the CAN controller: CAN Controller
• eNVM: Embedded Nonvolatile Memory (eNVM) Controllers
In the UG0446: SmartFusion2 and IGLOO2 FPGA High Speed DDR Interfaces User Guide, refer to the
following chapters:
• MDDR: MDDR Subsystem
• FDDR: Fabric DDR Subsystem
Table 787 • Minimum Number of Checksum Bits Required Data
Width Checksum Bits
27 to 57 7
58 to 64 8
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