Microsemi SmartFusion2 - Functional Description; Architecture Overview; Table 139 AHB Bus Matrix Connectivity

AHB Bus Matrix
UG0331 User Guide Revision 15.0 211
7.1 Functional Description
This section provides a detailed description of the AHB bus matrix.
7.1.1 Architecture Overview
Figure 102, page 212 depicts the interconnection between the master stage blocks and the slave stage
blocks. The basic building blocks of the AHB bus matrix are the master stage block with an address
decoder and the slave stage block with a slave arbiter. Each master interfaces with the master stage
block and each slave interfaces with the slave stage block. The masters and slaves connect as shown in
Figure 101, page 210.
An address decoder sub-block in each master stage generates the slave select signal to the
corresponding slave. A slave arbiter sub-block in each slave stage generates the address-ready signal to
the selected master.
Reads or writes to areas not allowed cause the AHB bus matrix to complete the transaction with an
HRESP error indication. An error bit is set in the SW_ERRORSTATUS field of the MSS_EXTERNAL_SR
register. The following types of errors can occur:
• Write by an enabled master to a slave that is not RW
• Write by an enabled master to addresses not corresponding to a slave
• Write by the fabric master to the protected region
• Write by a disabled master to any location
Table 139 • AHB Bus Matrix Connectivity
Masters
M3
DCode
Bus
M3
ICode Bus
M3
System
Bus
System
Controller
HPDM
A FIC_0 FIC_1 MAC PDMA USB
MM1 MM0 MM2 MM9 MM3 MM4 MM5 MM6 MM7 MM8
Priority 1 2 3 4 444444
Arbitration Fixed Fixed Fixed Fixed WRR WRR WRR WRR WRR WRR
Slaves
eSRAM0 MS0RW RW RW RW RW RWRWRWRWRW
eSRAM1 MS1RW RW RW RW RW RWRWRWRWRW
eNVM_0 MS2 RW
1
1. Exercise caution when commanding the eNVM to program or erase data. Other masters in the system may not be aware that
the eNVM is unavailable if it is in a program or erase cycle. Microsemi recommends you use some form of software semaphore
to control access.
2 Low numbers in priority represent higher priority, with 1 being the highest priority.
R
1
RW
1
RW
1
R
1
RW
1
RW
1
RW
1
eNVM_1 MS3 RW
1
R
1
RW
1
RW
1
R
1
RW
1
RW
1
RW
1
FIC_0 MS4 RW RW RWRWRWRWRWRW
MAC MS5 RW RW RW RW
FIC_1 RW RW RW RW RW RW RW RW
SYSREG RW RW RW RW
APB_0 RW RW RW RW RW
APB_1 RW RW RW RW RW
APB_2 RW RW RW RW
USB RW RW RW RW
MSS DDR
Bridge
MS6 RW RWRWRWRWRW