Serial Peripheral Interface Controller
UG0331 User Guide Revision 15.0 537
14.4.3.16 SPI Status 8 Register
The following table describes the SPI status 8 (STAT8) register. This register allows the important status
bits to be read as a single 8-bit value. This reduces the overhead of checking the Status register bits
when an 8-bit processor is being used.
Table 516 • STAT8
Bit
Number
Equivalent STATUS
Register Bit
Position Name R/W
Reset
Value Description
[31:8] Reserved R/W 0 Software should not rely on the value of a
reserved bit. To provide compatibility with future
products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 14 ACTIVE R 0 SPI is still transmitting the data
6 13 SSEL R 0 Current state of SPI_X_SS[0]
5 3 TXUNDERRUN R 0 Transmit FIFO underflowed
4 2 RXOVERFLOW R 0 Receive FIFO overflowed
3 8 TXFIFOFUL R 0 Transmit FIFO is full
2 6 RXFIFOEMP R 0 Receive FIFO is empty
1 0 and 1 DONE R 0 The number of request frames have been
transmitted and received.
0 12 FRAMESTART R 0 Next frame in receive FIFO was received after
SPI_X_SS[x] went active (command frame).
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