Microsemi SmartFusion2 - Table 368 FIFO_CFG5; Table 369 FIFO_RAM_ACCESS0

Ethernet MAC
UG0331 User Guide Revision 15.0 414
20 hstsrfullclr 0x0 This bit should be written when it is desired to clear the srfull
indicator bit. After the hstfullclr assertion, the srfull should be
read until it becomes unasserted.
19 cfgbytmode 0x0 This bit should be asserted when the PE-MCXMAC is configured
for GMII mode.
18 hstdrplt64 0x0 Setting this bit causes the frame to be dropped if a receive frame
is less than 64 bytes in length.
[17:0] hstfltrfrmdc 0X3FFFF These configuration bits indicate which receive statistics vectors
are don’t care for A-MCXFIFO frame drop circuitry. Receive
statistics vector indicates the characteristics of the current
receive frame.
Setting of the hstfltrfrmdc bit, indicates a don’t care for the
receive statistics vector bit. These bits corresponds to receive
statistics vector on a one per one basis. The hstfltrfrmdc bit and
their corresponding receive statistics vector is as follows:
BitDescription
17: System Receive unicast Address
16: Truncated Frame.
15:Receive long event.
14: VLAN Tagged frame: frame’s length/type field contained
0x8100 which is the VLAN protocol identifier.
13: Frame was Unsupported Op-code.
12:Frame was a PAUSE control frame
11:Long Event detected
10:Frame contained a dribble nibble
9:Broadcast address detected
8:Multicast address detected
7:Reception OK
6:Length/Type field was neither a length nor type
5:Frame’s length field out of range.
4:Frame contained a CRC Error.
3:Frame contained a code error.
2:False carrier previously seen
1:RX_DV event previously seen
0: Whether or not a prior packet was dropped
Table 369 • FIFO_RAM_ACCESS0
Bit Number Name Reset Value Description
31 hsttramwreq 0x0 Host transmit RAM write request
30 hsttramwack 0x0 Host transmit RAM write acknowledge
[29:24] Reserved 0x0 Reserved
[23:16] hsttramwdat
[39:32]
0x0 Host transmit RAM write data
This is the upper byte of the transmit FIFO RAM data that is
written at the address of hsttramwadx[10:0], if hsttramwadx[12]
is negated and hsttramwreq is asserted.
[15:13] Reserved 0x0 Reserved
[12:0] hsttramwadx 0x0 Host transmit RAM write address
Table 368 • FIFO_CFG5 (continued)