Microsemi SmartFusion2 - About the Instruction Descriptions

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 51
• any constant of the form 0xXY00XY00
• any constant of the form 0xXYXYXYXY
In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values. These are
described in the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS , MVNS , ANDS , ORRS , ORNS , EORS , BICS ,
TEQ or TST , the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can
be produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any
other constant.
Instruction substitution
Your assembler might be able to produce an equivalent instruction in cases where you specify a constant
that is not permitted. For example, an assembler might assemble the instruction
CMP Rd , #0xFFFFFFFE as
the equivalent instruction CMN Rd , #0x2 .
3.6.3.3.2 Register with Optional Shift
You specify an Operand2 register in the form:
Rm {, shift}
where:
Rm: is the register holding the data for the second operand.
shift: is an optional shift to be applied to Rm. It can be one of:
ASR #n: arithmetic shift right
n bits, 1  n  32.
LSL #n: logical shift left n bits, 1  n  31.
LSR #n: logical shift right n bits, 1  n  32.
ROR #n: rotate right n bits, 1  n  31.
RRX: rotate right one bit, with extend.
-: if omitted, no shift occurs, equivalent to LSL #0.
If you omit the shift, or specify
LSL #0 , the instruction uses the value in Rm .
If you specify a shift, the shift is applied to the value in
Rm , and the resulting 32-bit value is used by the
instruction. However, the contents in the register
Rm remains unchanged. Specifying a register with shift
also updates the carry flag when used with certain instructions. For information on the shift operations
and how they affect the carry flag, refer to Shift Operations, page 52.
3.6.3.4 Shift Operations
Register shift operations move the bits in a register left or right by a specified number of bits, the shift
length. Register shift can be performed:
• directly by the instructions
ASR , LSR , LSL , ROR , and RRX , and the result is written to a destination
register
• during the calculation of Operand2 by the instructions that specify the second operand as a register
with shift, refer to Flexible Second Operand, page 51. The result is used by the instruction.
The permitted shift lengths depend on the shift type and the instruction, refer to the individual instruction
description or Flexible Second Operand, page 51. If the shift length is 0, no shift occurs. Register shift
operations update the carry flag except when the specified shift length is 0. The following sub-sections
describe the various shift operations and how they affect the carry flag. In these descriptions,
Rm is the
register containing the value to be shifted, and
n is the shift length.
3.6.3.4.1 ASR
Arithmetic shift right by n bits moves the left-hand 32 - n bits of the register Rm , to the right by n places, into
the right-hand 32 - n bits of the result. And it copies the original bit[31] of the register into the left-hand n
bits of the result. Refer to Figure 18, page 53.