Microsemi SmartFusion2 - Figure 293 FIC_2_APB_M_PRESET_N Generation; Table 647 GPIO_OUT Bank Reset Generation

Reset Controller
UG0331 User Guide Revision 15.0 659
The generation of FIC_2_APB_M_PRESET_N is shown in the following figure.
Figure 293 • FIC_2_APB_M_PRESET_N Generation
21.2.6.5 MSS GPIO Bank Resets Generator
The MSS GPIOs bank can be selectively reset through SYSREG or from flash bits. The GPOUT register
is split into four banks of one byte each and each bank has a reset signal.
The Reset Controller receives two SYSREG bits: Soft reset and Select. The Select bit determines the
reset source for the associated MSS GPOUT byte. The source can be either of the following:
• Soft reset from system register
• Hard reset derived from either power-on reset or the GPIO_RESET_N signal from the FPGA fabric.
The GPIO_SYSRESET_SEL_CR register (defined in Tabl e 64 8 , page 669) can be configured to select
one of the reset inputs. The entire GPIO bank can be kept in reset by asserting the
MSS_GPIO_SOFTRESET bit in SOFT_RESET_CR (defined in Table 648, page 669) of SYSREG. A
particular GPIO byte can be reset by asserting the corresponding MSS_GPIO_xx_xx_SOFTRESET bit in
SOFT_RESET_CR (defined in Tabl e 64 8 , page 669) of SYSREG.
The generation of GPOUT bank resets for flash bit control is shown in the following figure. Only one
GPOUT byte bank reset is shown; the resets for other banks are generated in a similar way.
The flash bits to the MSS GPIO are used to initialize the GPOUT byte on assertion of reset. When reset
is deasserted, the GPOUT byte will follow the Switch Input (D). When one of the flash bits is
deasserted, the associated GPIO_OUT pins are initialized to '0'. The following table explains the
generation of GPIO_OUT. MSS_GPIO_xx_xx_DEF bits are in the MSS_GPIO_DEF register of SYSREG.
Table 647 • GPIO_OUT Bank Reset Generation
MSS_GPIO_xx_xx_DEF Reset Controller o/p GPIO_OUT o/p
000
01D
101
11D
4FFs
M3_CLK
SYSRESET_N
1
FIC_2_APB_M_PCLK
DFF