Microsemi SmartFusion2 - Table 222 RX_CSRL_REG (Peripheral)

Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 324
10.3.6.11 RX_CSRL_REG (in Peripheral mode) Bit Definitions
10.3.6.12 RX_CSRL_REG (in Host mode) Bit Definitions
Table 222 • RX_CSRL_REG (Peripheral)
Bit
Number Name
Reset
Value Function
7 ClrDataTog 0 The Cortex-M3 processor (or fabric master) writes a 1 to this bit to reset the
endpoint data toggle to 0.
6 SentStall 0 This bit is set when a STALL handshake is transmitted. The Cortex-M3 processor
(or fabric master) should clear this bit.
5 SendStall 0 The Cortex-M3 processor (or fabric master) writes a 1 to this bit to issue a STALL
handshake. The Cortex-M3 processor (or fabric master) clears this bit to terminate
the stall condition.
This bit has no effect where the endpoint is being used for ISO transfers.
4 FlushFIFO 0 The Cortex-M3 processor (or fabric master) writes a 1 to this bit to flush the latest
packet from the endpoint receive FIFO. The FIFO pointer is reset, the RxPktRdy bit
(bit 0 of this register) is cleared.
FlushFIFO should only be used when RxPktRdy is set. At other times, it may cause
data to be corrupted.
If the FIFO is double-buffered, FlushFIFO may need to be set twice to completely
clear the FIFO.
3 DataError 0 This bit is set when RxPktRdy (bit 0 of this register) is set if the data packet has a
CRC or bit-stuff error. It is cleared when RxPktRdy is cleared.
This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it
always returns zero.
2 OverRun 0 This bit is set if an OUT packet cannot be loaded into the receive FIFO. The Cortex-
M3 processor (or fabric master) should clear this bit.
This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it
always returns zero.
1 FIFOFull 0 This bit is set when no more packets can be loaded into the receive FIFO.
0 RxPktRdy 0 This bit is set when a data packet has been received. The Cortex-M3 processor (or
fabric master) should clear this bit when the packet has been unloaded from the
receive FIFO. An interrupt is generated when the bit is set.
Table 223 • RX_CSRL_REG (Host)
Bit
Number Name
Reset
Value Function
7 ClrDataTog 0 The Cortex-M3 processor (or fabric master) writes a 1 to this bit to reset the
endpoint data toggle to 0.
6 RxStall 0 When a STALL handshake is received, this bit is set and an interrupt is
generated. The Cortex-M3 processor (or fabric master) should clear this bit.
5 ReqPkt 0 The Cortex-M3 processor (or fabric master) writes a 1 to this bit to request an IN
transaction. It is cleared when RxPktRdy is set.