Microsemi SmartFusion2 - Dfr; Dlr; Dmr; Table 471 DLR

MMUART Peripherals
UG0331 User Guide Revision 15.0 493
The special case of the integer divisor value (DLR+DMR) equal to one is not allowed in fractional mode
as maximum error comes when the value is one. Therefore use integer divisor values of two or more
when using fractional mode.
Baud Rate Registers (DLR, DMR, and DFR)
As explained earlier, the divisor value has an integer part and a fractional part. Calculate the 6-bit number
(k) which is the fractional divisor in DFR register by taking the fractional part of the required baud rate
divisor and multiplying it by 64 (that is, 2
n
, where n is the fractional part which is 6) and adding 0.5 to
account for rounding errors:
k = integer (fractional part of divisor value × 2
n
+ 0.5)
For example, to generate the baud rate of 134.5 the reference clock is 18.432 MHz.
F
APBCLK
= 18.432 MHz, Fractional BR = 134.5,
Hence, calculate the divisor value = (18.432 × 10
6
) / (16 × 134.5) = 8,565.05
The integer part of divisor = 8565 and fractional part of divisor = 0.05
Therefore, the fractional part, k = integer ((0.05 × 64) + 0.5) = 3.7 ~ = 4
Table 471 • DLR
Bit
Number Name R/W
Reset
Value Description
[7:0] DLR R/W 0x01 This divisor latch LSB register (DLR) holds the LSB of the integer divisor
value used to calculate the baud rate. The baud rate can be calculated using
EQ 1, 2, 3, or 4.
Table 472 • DMR
Bit
Number Name R/W
Reset
Value Description
[7:0] DMR R/W 0x00 This divisor latch MSB register (DMR) holds the MSB of the integer divisor
value used to calculate the baud rate. The baud rate can be calculated using
EQ 1, 2, 3, or 4.
Table 473 • DFR
Bit
Number Name R/W
Reset
Value Description
[5:0] DFR R/W 0x00 The fractional divisor register (DFR) is used to store the fractional divisor
used to calculate the fractional baud rate value in 1/64
th
.
0x0: 0/64
0x1: 1/64
….
0x3F: 63/64