Microsemi SmartFusion2 - Figure 45 HFSR Bit Assignments; Table 66 UFSR Bit Assignments

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 116
The UFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit
that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.
3.7.2.14 HardFault Status Register
The HFSR gives information about events that activate the HardFault handler. See the register summary
in Table 50, page 102 for its attributes.
This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any
bit clears that bit to 0. The bit assignments are:
Figure 45 • HFSR Bit Assignments
[8] UNALIGNED Unaligned access UsageFault:
0: no unaligned access fault, or unaligned access trapping not enabled
1: the processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the CCR to
1, see Configuration and Control Register, page 109.
Unaligned
LDM , STM , LDRD , and STRD instructions always fault irrespective of the
setting of UNALIGN_TRP.
[7:4] Reserved.
[3] NOCP No coprocessor UsageFault. The processor does not support coprocessor
instructions:
0: no UsageFault caused by attempting to access a coprocessor
1: the processor has attempted to access a coprocessor.
[2] INVPC Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN:
0: no invalid PC load UsageFault
1: the processor has attempted an illegal load of EXC_RETURN to the PC, as a result
of an invalid context, or an invalid EXC_RETURN value.
When this bit is set to 1, the PC value stacked for the exception return points to the
instruction that tried to perform the illegal load of the PC.
[1] INVSTATE Invalid state UsageFault:
0: no invalid state UsageFault
1: the processor has attempted to execute an instruction that makes illegal use of the
EPSR.
When this bit is set to 1, the PC value stacked for the exception return points to the
instruction that attempted the illegal use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
[0] UNDEFINSTR Undefined instruction UsageFault:
0: no undefined instruction UsageFault
1: the processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the exception return points to the
undefined instruction.
An undefined instruction is an instruction that the processor cannot decode.
Table 66 • UFSR Bit Assignments (continued)
Bits Name Function
31 30 210
Reserved
29
DEBUGEVT
FORCED VECTTBL
Reserved