Embedded SRAM (eSRAM) Controllers
UG0331 User Guide Revision 15.0 191
6.2.2 Modes of Operation
There are two modes of operation for the eSRAM controller: SECDED-ON and SECDED-OFF.
6.2.2.1 SECDED-ON
SECDED mode can be turned ON by configuring the EDAC_CR register. The total available memory for
each eSRAM in this mode is 32 KB. The eSRAM controller generates 7 check bits for every 32 bits of
data, so for every 32 bits of data there will be 7 bits of encoded data. The 7 bits of ECC allow 1-bit
correction and 2-bit detection on the user data and ECC field. The 32 data bits and 7 bits of ECC are
written to the memory with zero wait states. Byte and half-word write operations are done using a
read-modify-write operation. The read-modify-write operation requires an additional wait state for byte
and half-word write operations.
In the case of a 1-bit error, the previous 32 bits of data and ECC value are read and correction takes
place automatically. The complete 32 bits plus ECC is rewritten. For byte and half-word write operations,
there is one wait state required as the ECC value is read and corrected for the byte/half-word.
When a 2-bit error is detected during a read cycle for 32-bit data, HRESP is asserted High for two clock
cycles and at the same time HREADYOUT goes Low for one clock cycle to indicate an error.
When a 2-bit error is detected during the read part of a read-modify-write byte or half-word operation,
HRESP is asserted High.
6.2.2.2 SECDED-OFF
SECDED mode can be turned OFF by configuring the EDAC_CR register. The total available memory for
each eSRAM is 40 KB. 1-bit correction and 2-bit detection on the user data is not applicable in this mode.
6.2.3 Pipeline Modes and Wait States for Read and Write Operations
When any master on the AHB bus matrix operates at a high frequency greater than 100 MHz, and is
accessing eSRAM, an extra clock cycle is needed for transactions. An optional pipeline can be enabled
on the Read data bus; this adds a clock cycle to all read operations. The pipeline is enabled by default in
both SECDED-ON and SECDED-OFF modes. When the master on the AHB bus matrix operates at low
frequency, less than 100 MHz, the pipeline can be turned off. Refer to Tab le 1 26, page 201 for
information on pipeline enable/ disable.
The actual frequency at which this is possible is specified in the AC characteristics table of
DS0451: IGLOO2 and SmartFusion2 Datasheet. When the pipeline is disabled, the number of wait states
is less, increasing throughput of read operations.
2047 1FFD 5FFF 5FFE 5FFD 5FFC 1FFC 1FFF 1FFE 1FFD 1FFC
2048 0003 6003 6002 6001 6000 0002 2003 2002 2001 2000
2049 0007 6007 6006 6005 6004 0006 2007 2006 2005 2004
4094 1FFB 7FFB 7FFA 7FF9 7FF8 1FFA 3FFB 3FFA 3FF9 3FF8
4095 1FFF 7FFF 7FFE 7FFD 7FFC 1FFE 3FFF 3FFE 3FFD 3FFC
Table 120 • SRAM Organization in SECDED-OFF Mode (continued)
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