Microsemi SmartFusion2 - Table 730 MM3_6_7_8_SECURITY; Security Configuration Register for Masters 3, 6, 7, and 8

System Register Block
UG0331 User Guide Revision 15.0 719
22.3.73 Security Configuration Register for Masters 3, 6, 7, and 8
7 MM4_5_DDR_FIC_MS3_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to
slave 3 (eNVM1). If not set, masters 4, 5, and DDR_FIC
will not have write access to slave 3.
6 MM4_5_DDR_FIC_MS3_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to
slave 3 (eNVM1). If not set, masters 4, 5, and DDR_FIC
will not have read access to slave 3.
5 MM4_5_DDR_FIC_MS2_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to
slave 2 (eNVM0). If not set, masters 4, 5, and DDR_FIC
will not have write access to slave 2.
4 MM4_5_DDR_FIC_MS2_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to
slave 2 (eNVM0). If not set, masters 4, 5, and DDR_FIC
will not have read access to slave 2.
3 MM4_5_DDR_FIC_MS1_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to
slave 1 (eSRAM1). If not set, masters 4, 5, and
DDR_FIC will not have write access to slave 1.
2 MM4_5_DDR_FIC_MS1_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to
slave 1 (eSRAM1). If not set, masters 4, 5, and
DDR_FIC will not have read access to slave 1.
1 MM4_5_DDR_FIC_MS0_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to
slave 0 (eSRAM0). If not set, masters 4, 5, and
DDR_FIC will not have write access to slave 0.
0 MM4_5_DDR_FIC_MS0_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to
slave 0 (eSRAM0). If not set, masters 4, 5, and
DDR_FIC will not have read access to slave 0.
Table 730 • MM3_6_7_8_SECURITY
Bit
Number Name
Reset
Value Description
[31:10] Reserved 0
9 MM3_6_7_8_MS6_ALLOWED_W 1 Write security bits for masters 3, 6, 7, and 8 to slave 6 (MSS
DDR bridge). If not set, masters 3, 6, 7, and 8 will not have
write access to slave 6.
8 MM3_6_7_8_MS6_ALLOWED_R 1 Read security bits for masters 3, 6, 7, and 8 to slave 6 (MSS
DDR bridge). If not set, masters 3, 6, 7, and 8 will not have
read access to slave 6.
7 MM3_6_7_8_MS3_ALLOWED_W 1 Write security bits for masters 3, 6, 7, and 8 to slave 3
(eNVM1). If not set, masters 3, 6, 7, and 8 will not have write
access to slave 3.
6 MM3_6_7_8_MS3_ALLOWED_R 1 Read security bits for masters 3, 6, 7, and 8 to slave 3
(eNVM1). If not set, masters 3, 6, 7, and 8 will not have read
access to slave 3.
5 MM3_6_7_8_MS2_ALLOWED_W 1 Write security bits for masters 3, 6, 7, and 8 to slave 2
(eNVM0). If not set, masters 3, 6, 7, and 8 will not have write
access to slave 2.
Table 729 • MM4_5_DDR_FIC_SECURITY/MM4_5_FIC64_SECURITY (continued)
Bit
Number Name
Reset
Value Description