Microsemi SmartFusion2 - Figure 291 MDDR_APB_RESET_N Generation; Figure 292 WDOG_RESET_N Generation

Reset Controller
UG0331 User Guide Revision 15.0 658
The generation of MDDR_APB_RESET_N is shown in the following figure.
Figure 291 • MDDR_APB_RESET_N Generation
The Reset Controller drives a synchronized reset to the APB logic of the MDDR subsystem.
21.2.6.3 Watchdog Resets
21.2.6.3.1 WDOG_RESET_N
The WDOG_BLOCK_RESET_N signal is synchronized on M3_CLK and CLK_RCOSC, then gated with
WDOG_ENABLE. The gating ensures that if WDOG_ENABLE is not asserted, WDOG_RESET_N will be
asserted. This reset is used to hold the watchdog logic clocked by M3_CLK in reset. The
WDOG_ENABLE bit is in the watchdog configuration register (WDOG_CR) as defined in Table 648,
page 669) of the SYSREG.
The generation of WDOG_RESET_N is shown in the following figure.
Figure 292 • WDOG_RESET_N Generation
The Reset Controller drives the reset input of the Watchdog Timer.
21.2.6.3.2 PO_RESET_RCOSC_N
The PO_RESET_RCOSC_N is a synchronized version of the PO_RESET_N signal on CLK_RCOSC. It
asserts asynchronously and negates synchronously to CLK_RCOSC.
This is a power-on reset signal to the Watchdog Timer.
21.2.6.4 Clock Controller Reset
21.2.6.4.1 CC_RESET_N
The CC_RESET_N is generated on the assertion of PO_RESET_N. This is a power-on reset signal to
the fabric alignment clock controller (FACC).
21.2.6.4.2 FIC_2_APB_M_PRESET_N
This is an APB reset signal to the FPGA fabric interface.
SYSRESET_N is synchronized on FIC_2_APB_M_PCLK generated in the MSS CCC, which is driven to
the FPGA fabric and then the synchronized reset is again flopped on the negative edge of M3_CLK.
1
0
MDDR_APB_S_RESET_N
SYSRESET_N
MDDR_CONFIG_LOCAL
MDDR_APB_RESET_N
8FFs
4FFs
WDOG_ENABLE
WDOG_RESET_N
CLK_RCOSC
1
1
M3_CLK
SYSRESET_N
SC_MSS_RESET_M3_CLK_N
MSS_RESET_F2M_M3_CLK_N
SYS_RESETREQ_N
LOCKUP_N