Microsemi SmartFusion2 - Figure 181 Sample Time Correction with Fractional Baud Rate

MMUART Peripherals
UG0331 User Guide Revision 15.0 476
13.2.4.1.1 Fractional Baud Rate Generation–Asynchronous Mode
The following figure depicts accumulative baud rate difference error in the Asynchronous mode. It also
describes how fractional baud rate generation reduces this error by adding wait times, in the essence of
forming a new average baud rate value that is between two given integer baud rate values.
Specifically, fractional baud rate generation modulates the integer baud rate with the integer baud rate +
1/16
th
of a Tbit time (bit transmit time) to yield a time averaged fractional value. The fractional resolution
is 1/64
th
resolution. A 6-bit phase accumulator evenly distributes the fractional value over 64 Tbit times.
Figure 181 • Sample Time Correction with Fractional Baud Rate
The following equation is used to calculate the fractional baud rate:
where,
APB_X_CLK: Input reference clock (APB_0_CLK for MMUART_0 and APB_1_CLK for MMUART_1)
DMR: Divisor latch for MSB
DLR: Divisor latch for LSB
DFR: Fractional divisor register
If a baud rate value of 1 and 1/64th (1.015625) is required, set the "DLR" to 1, the "DMR" to 0, and "DFR"
to 1. Following examples illustrate the use of fractional baud rate.
?
?
Received Baud Rate Matches Transmitted Baud Rate through injection of single APB CLK cycle
waits in the baud generation
Received Baud Rate Faster Than Transmitted Baud Rate
Received Baud Rate Matches Transmitted Baud Rate
*Accumulative Error is Reduced resulting in no Sample Error
*Accumulative Error results in Error on the Last Bits
*No Sample Error
Rxd
Rxd
Rxd
Sample Times
Stop
Bit
Stop
Bit
Stop
Bit
Start
Bit
Start
Bit
Start
Bit
Sample Times
Sample Times
Wait Times
d0 d1 d2 d3 d4 d5 d6 d7 p0
d0 d1 d2 d3 d4
d5
d6 d7
p0
d0 d1 d2 d3 d4
d5
d6 d7
p0
FractionalBaudRate
ABP X CLK
16 DMR DLR DFR 64++
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