Microsemi SmartFusion2 - Table 150 HPDMAEDR_REG

High Performance DMA Controller
UG0331 User Guide Revision 15.0 248
5 HPDMAEDR_DCP_CMPLET[1] 0 Descriptor 1 transfer complete.
1: Descriptor 1 transfer completed successfully.
0: Descriptor 1 transfer not completed.
When the descriptor 1 transfer is completed, either
with transfer error or transfer done, the HPDMA
controller asserts this bit High.
This bit is cleared on writing ‘1’ to the
HPDMAICR_CLR_XFR_INT[1] bit of the HPDMA
Interrupt Clear register or when the
HPDMACR_DCP_VALID[1] bit of the descriptor 1
Control register is set.
6 HPDMAEDR_DCP_CMPLET[2] 0 Descriptor 2 transfer complete.
1: Descriptor 2 transfer completed successfully
0: Descriptor 2 transfer not completed
When the descriptor 2 transfer is completed, either
with transfer error or transfer done, the HPDMA
controller asserts this bit High.
This bit is cleared on writing ‘1’ to the
HPDMAICR_CLR_XFR_INT[2] bit of the HPDMA
Interrupt Clear register or when the
HPDMACR_DCP_VALID[2] bit of the descriptor 2
Control register is set.
7 HPDMAEDR_DCP_CMPLET[3] 0 Descriptor 3 transfer complete.
1: Descriptor 3 transfer completed successfully
0: Descriptor 3 transfer not completed
When the descriptor 3 transfer is completed, either
with transfer error or transfer done, the HPDMA
controller asserts this bit High.
This bit is cleared on writing ‘1’ to the
HPDMAICR_CLR_XFR_INT[3] bit of the HPDMA
Interrupt Clear Register or when the
HPDMACR_DCP_VALID[3] bit of the descriptor 3
control register is set.
8 HPDMAEDR_DCP_ERR[0] 0 Descriptor 0 transfer error.
1: Descriptor 0 transfer error
0: No descriptor 0 transfer error
This bit is asserted High if an error occurs during the
descriptor 0 transfer at either source or destination
end. This bit is cleared on writing ‘1’ to the
HPDMAICR_CLR_XFR_INT[0] bit of the HPDMA
Interrupt Clear register or when the
HPDMACR_DCP_VALID[0] bit of the descriptor 0
control register is set.
Table 150 • HPDMAEDR_REG (continued)
Bit
Number Name
Reset
Value Description