High Performance DMA Controller
UG0331 User Guide Revision 15.0 249
9 HPDMAEDR_DCP_ERR[1] 0 Descriptor 1 transfer error.
1: Descriptor 1 transfer error
0: No descriptor 1 transfer error
This bit is asserted High, if an error occurs during the
descriptor 1 transfer at either source or destination
end. This bit is cleared on writing ‘1’ to
HPDMAICR_CLR_XFR_INT[1] of the HPDMA
Interrupt Clear register, or when the
HPDMACR_DCP_VALID[1] bit of Descriptor 1 control
register is set.
10 HPDMAEDR_DCP_ERR[2] 0 Descriptor 2 transfer error.
1: Descriptor 2 transfer error
0: No descriptor 2 transfer error
This bit is asserted High, if an error occurs during the
descriptor 2 transfer at either source or destination
end. This bit is cleared on writing ‘1’ to the
HPDMAICR_CLR_XFR_INT[2] bit of the HPDMA
Interrupt Clear register, or when the
HPDMACR_DCP_VALID[2] bit of the descriptor 2
control register is set.
11 HPDMAEDR_DCP_ERR[3] 0 Descriptor 3 transfer error.
1: Descriptor 3 transfer error
0: No descriptor 3 transfer error
This bit is asserted High, if an error occurs during the
descriptor 3 transfer at either source or destination
end. This bit is cleared on writing ‘1’ to
HPDMAICR_CLR_XFR_INT[3] of the HPDMA
Interrupt Clear register, or when the
HPDMACR_DCP_VALID[3] bit of the descriptor 3
control register is set.
12
HPDMAEDR_DCP_NON_WORD_ERR[0] 0 Descriptor 0 non-word aligned transfer size error.
1: Descriptor 0 non-word aligned transfer size error
0: No non-word aligned transfer size error
This bit is asserted High, if non-word aligned value is
configured in descriptor 0 transfer size field. This bit is
cleared on writing ‘1’ to
HPDMAICR_NON_WORD_INT[0] of the HPDMA
Interrupt Clear register, or when the
HPDMACR_DCP_VALID[0] bit of the descriptor 0
Control register is set or when the
HPDMACR_DCP_CLR[0] bit of the HPDMA
Controller register is set.
In this case, HPDMA will continue the transfer by
ignoring the 2 LSBs of the transfer size field.
Table 150 • HPDMAEDR_REG (continued)
Bit
Number Name
Reset
Value Description
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