High Performance DMA Controller
UG0331 User Guide Revision 15.0 250
13 HPDMAEDR_DCP_NON_WORD_ERR[1] 0 Descriptor 1 non-word aligned transfer size error.
1: Descriptor 1 non-word aligned transfer size error
0: No non-word aligned transfer size error
This bit is asserted High if a non-word aligned value is
configured in the descriptor 1 transfer size field.
This bit is cleared on writing ‘1’ to
HPDMAICR_NON_WORD_INT[1] of the HPDMA
Interrupt Clear register, or when the
HPDMACR_DCP_VALID[1] bit of the descriptor 1
Control register is set, or when the
HPDMACR_DCP_CLR[1] bit of the HPDMA
Controller register is set.
In this case, HPDMA will continue the transfer by
ignoring the 2 LSBs of the transfer size filed.
14 HPDMAEDR_DCP_NON_WORD_ERR[2] 0 Descriptor 2 non-word aligned transfer size error.
1: Descriptor 2 non-word aligned transfer size error
0: No non-word aligned transfer size error
This bit is asserted High if a non-word aligned value is
configured in the descriptor 2 transfer size field.
This bit is cleared on writing ‘1’ to
HPDMAICR_NON_WORD_INT[2] of the HPDMA
Interrupt Clear register, or when the
HPDMACR_DCP_VALID[2] bit of the descriptor 2
Control register is set, or when the
HPDMACR_DCP_CLR[2] bit of the HPDMA
Controller register is set.
In this case, HPDMA will continue the transfer by
ignoring the 2 LSBs of the transfer size field.
15 HPDMAEDR_DCP_NON_WORD_ERR[3] 0 Descriptor 3 non-word aligned transfer size error.
1: Descriptor 3 non-word aligned transfer size error
0: No non-word aligned transfer size error
This bit is asserted High, if a non-word aligned value
is configured in the descriptor 3 transfer size field.
This bit clears on writing ‘1’ to
HPDMAICR_NON_WORD_INT[3] of the HPDMA
Interrupt Clear register, or when the
HPDMACR_DCP_VALID[3] bit of the descriptor 3
Control register is set, or when the
HPDMACR_DCP_CLR[3] bit of the HPDMA
Controller register is set.
In this case, HPDMA will continue the transfer by
ignoring the 2 LSBs of transfer size field.
[31:16] Reserved 0 Software should not rely on the value of a reserved
bit. To provide compatibility with future products, the
value of a reserved bit should be preserved across a
read-modify-write operation.
Table 150 • HPDMAEDR_REG (continued)
Bit
Number Name
Reset
Value Description
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