Watchdog Timer
UG0331 User Guide Revision 15.0 639
Table 638 • WDOGMVRP
Bit Number Name Reset Value Description
[31:0] WDOGMVRP WDOGMVRP This register contains the maximum value for which refreshing is
permitted.
If the watchdog timer is refreshed (by writing to the
WDOGREFRESH register) while the counter value is greater
than the value in the WDOGMVRP, then a reset/interrupt is
generated. This read only register is loaded with the user flash bit
value written in the WDOGMVRP[31:0] system register.
Table 639 • WDOGREFRESH
Bit Number Name Reset Value Description
[31:0] WDOGREFRESH N/A This is a write only register which reads as zero. Writing the
value 0xAC15DE42 to this register causes the counter to be
refreshed with the value in the WDOGLOAD register.
If this register is written to, while the current value of the counter
is greater than the value in the WDOGMVRP register, the
counter is refreshed and a reset or timeout interrupt is generated
(depending on the MODE bit of the WDOGCONTROL). While
the counter value is greater than the WDOGMVRP, there is
effectively a time window in which it is forbidden to refresh the
watchdog timer.
When the counter is in between the WDOGMVRP level and 0,
the watchdog timer is in a time window where it is permitted for it
to be refreshed.
It is possible to avoid having the forbidden and permitted time
windows for refreshing the watchdog timer by setting the value of
the WDOGMVRP to a value greater than that stored in the
WDOGLOAD.
Table 640 • WDOGENABLE
Bit Number Name Reset Value Description
[31:1] Reserved 0x0 Reserved
0 ENABLE WDOGENABLE Enable bit for watchdog timer.
This bit holds the value of the USER FLASH bit written in the
WDOGENABLE bit of the WDOG_CR system register.
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