Microsemi SmartFusion2 - Figure 299 Timing for Reset Signals Initiated by the Assertion of POWER_N_RESET_N; Figure 300 Timing for Reset Signals Initiated by the Assertion of FIC_2_APB_M_PRESET_N; Timing Diagrams

Reset Controller
UG0331 User Guide Revision 15.0 664
21.3.3 Timing Diagrams
The following figures show the timing of reset signals for reset sequences initiated by the assertion of
POWER_ON_RESET_N, FIC_2_APB_M_PRESET_N, EXT_RESET_IN_N, and
USER_FAB_RESET_IN_N signals.
Figure 299 • Timing for Reset Signals Initiated by the Assertion of POWER_N_RESET_N
Figure 300 • Timing for Reset Signals Initiated by the Assertion of FIC_2_APB_M_PRESET_N
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