Microsemi SmartFusion2 - Interrupt Generation; Figure 169 Interrupt Generation

CAN Controller
UG0331 User Guide Revision 15.0 441
12.2.4 Interrupt Generation
The interrupt int_n is asserted, if a particular interrupt status bit and the respective enable bit are set. The
following figure shows how the system interrupt is generated.
Figure 169 • Interrupt Generation
INT_STATUS[3]
INT_STATUS[2]
INT_STATUS[4]
INT_STATUS[5]
INT_STATUS[6]
INT_STATUS[7]
INT_STATUS[8]
INT_STATUS[9]
INT_STATUS[10]
INT_STATUS[11]
INT_STATUS[13]
INT_STATUS[12]
INT_STATUS[14]
INT_STATUS[15]
INT_ENABLE[2]
INT_ENABLE[4]
INT_ENABLE[3]
INT_ENABLE[5]
INT_ENABLE[6]
INT_ENABLE[7]
INT_ENABLE[9]
INT_ENABLE[10]
INT_ENABLE[11]
INT_ENABLE[12]
INT_ENABLE[14]
INT_ENABLE[15]
INT_ENABLE[13]
INT_ENABLE[8]
RxIntEbI[RX_MSG0]
MsgAv[RX_MSG0]
RxIntEbI[RX_MSG31]
MsgAv[RX_MSG31]
INT_ENABLE[12]
INT_ENABLE[11]
TxIntEbI[TX_MSG31]
TxIntEbI[TX_MSG0]
TxReq done
[TX_MSG0]
TxReq done
[TX_MSG31]
arb_loss
ovr_load
Bit_err
stuff_err
ack_err
form_err
crc_err
buss_off
rx_msg_loss
tx_msg
rx_msg
rtr_msg
stuck_at_0
sst_failure
Int_enbl
Int_n
>=1
>=1
rx_msg
tx_msg
>=1