Microsemi SmartFusion2 - Table 355 MII_ADDRESS

Ethernet MAC
UG0331 User Guide Revision 15.0 407
Table 355 • MII_ADDRESS
Bit Number Name Reset Value Description
[31:13] Reserved 0x0 Reserved
[12:8] PHY ADDRESS 0x00 This field represents the 5-bit PHY address field used in
Mgmt cycles. Up to 31 PHYs can be addressed (0 is
reserved).
[4:0] REGISTER
ADDRESS
0x00 This field represents the 5-bit register address field of Mgmt
cycles. Up to 32 registers can be accessed.
Table 356 • MII_CTRL
Bit Number Name Reset Value Description
[31:16] Reserved 0x0 Reserved
[15:0]
MII MGMT
CONTROL
0x0
When written, an MII Mgmt write cycle is performed using the
16-bit data and the pre-configured PHY and register addresses
from the MII Mgmt Register (0x0A).
Table 357 • MII_STATUS
Bit Number Name Reset Value Description
[31:16] Reserved 0x0 Reserved
[15:0] MII MGMT STATUS
(PHY STATUS)
0x0 Following an MII Mgmt read cycle, the 16-bit data can be read
from this location.
Table 358 • MII_INDICATORS
Bit Number Name Reset Value Description
[31:3] Reserved 0x0 Reserved
2 NOT VALID 0x0 When ‘1’ is returned, this indicates MII Mgmt Read cycle is
not completed and the Read Data is not yet validated.
1 SCANNING 0x0 When ‘1’ is returned, this indicates a scan operation
(continuous MII Mgmt Read cycles) is in progress.
0 BUSY 0x0 When ‘1’ is returned, this indicates MII Mgmt block is currently
performing an MII Mgmt read or write cycle.
Table 359 • INTERFACE_CTRL
Bit Number Name Reset Value Description
31 RESET
INTERFACE
MODULE
0x0 Setting this bit resets the interface module. Clearing this bit
allows for the normal operation. This bit can be used in the
place of bits 23, 15, and 7, when just 1 interface module is
connected.
[30:28] Reserved 0x0 Reserved