Microsemi SmartFusion2 - Figure 125 HPDMA Transfers Data between DDR Memory and MSS Internal Memory; Figure 126 HPDMA Transfers Data between SDR Memory and MSS Internal Memory

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High Performance DMA Controller

UG0331 User Guide Revision 15.0 243

2. To configure the HPDMA to transfer data between DDR memory and MSS internal memory, make

the selection in the MSS external memory configurator as shown in the following figure.

Figure 125 • HPDMA Transfers Data Between DDR Memory and MSS Internal Memory

3. To configure the HPDMA to transfer data between SDR memory and MSS internal memory, make

the selection in the MSS external memory configurator as shown in the following figure.

Figure 126 • HPDMA Transfers Data Between SDR Memory and MSS Internal Memory

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Default Chapter3
- Table of Contents3
Revision History35
- Revision 15.035
- Revision 14.035
- Revision 13.035
- Revision 12.035
- Revision 6.035
- Revision 11.036
- Revision 10.036
- Revision 9.036
- Revision 8.036
- Revision 7.036
- Revision 5.037
- Revision 4.037
- Revision 3.038
- Revision 2.038
- Revision 1.038
- Table 59 Table38
Cortex-M3 Processor Overview and Debug Features40
- Features40
- Functional Description41
- Figure 1 Cortex-M3 Processor R2P1 Block Diagram as Implemented in the Smartfusion2 Soc FPGA41
- Cortex-M3 Processor NVIC42
- Table 1 Cortex-M3 Processor Exceptions42
- Table 2 Cortex-M3 Processor Interrupts42
- Cortex-M3 Processor Systick Timer46
- Cortex-M3 Processor Debug Subsystem46
- Cortex-M3 Processor Port Descriptions49
- Table 4 Port Details of the Cortex-M3-Subsystem49
- How to Use the Cortex-M3 Processor and the Debug Subsystem50
Cortex-M3 Processor (Reference Material)52
- Figure 4 Cortex-M3 Processor Implementation52
- Cortex-M3 Processor Features and Benefits Summary53
- Integrated Configurable Debug53
- System Level Interface53
- Cortex-M3 Processor Core Peripherals54
- Cortex-M3 Processor Description54
- Cortex-M3 Processor Instruction Set81
- Cortex-M3 Processor Peripherals128
Cache Controller167
- Features167
- Figure 56 Cache Controller Interfaces to Cortex-M3 Processor, AHB Bus Matrix, and MDDR Bridge167
- Functional Description168
- How to Use Cache Controller177
Embedded NVM (Envm) Controllers179
- Features179
- Figure 65 Envm Connection to AHB Bus Matrix179
- Functional Description180
- Security193
- How to Use Envm199
- SYSREG Control Registers208
- Table 102 Available Apis for Envm208
- Table 103 SYSREG Control Registers208
- Envm_Status208
- Envm Control Registers214
Embedded SRAM (Esram) Controllers221
- Features221
- Functional Description222
  - Figure 95 Esram_0 and Esram_1 Connection to AHB Bus Matrix222
  - Table 118 Esram Block Sizes and Address Ranges222
  - Figure 96 Esram Controller Block Diagram223
  - Memory Organization224
  - Table 119 SRAM Organization in SECDED-ON Mode224
  - Table 120 SRAM Organization in SECDED-OFF Mode224
  - Table 461 ERROR_STATUS224
  - Modes of Operation225
  - Pipeline Modes and Wait States for Read and Write Operations225
  - Table 669 EDAC_CR225
  - Table 121 Wait States in Different Operation Modes226
- How to Use Esram228
- Figure 97 System Builder Window228
- Figure 98 System Builder - Microcontroller Tab229
- Figure 99 System Builder - SECDED Tab230
- Figure 100 System Builder - Security Tab231
- SYSREG Control Registers232
- Table 122 SYSREG Control Registers232
- Esram_Max_Lat232
- Esram_Pipeline_Cr232
- Esram0_Edac_Cnt232
- Esram1_Edac_Cnt232
- Esram0_Edac_Adr232
- Esram1_Edac_Adr232
- Mm0_1_2_Security232
- Mm4_5_Ddr_Fic_Security/Mm4_5_Fic64_Security232
  - Table 595 STATUS233
  - Table 731 MM9_SECURITY233
  - Table 123 ESRAM_CR234
  - Table 124 ESRAM_MAX_LAT234
  - Table 125 Esram Maximum Latency Values234
  - Table 126 ESRAM_PIPELINE_CR235
  - Table 130 ESRAM1_EDAC_ADR236
  - Table 132 MM4_5_DDR_FIC_SECURITY/MM4_5_FIC64_SECURITY237
- Table 134 MM9_SECURITY239
- Table 135 EDAC_SR240
- Table 136 CLR_EDAC_COUNTERS241
- Table 137 EDAC_IRQ_ENABLE_CR242
- Table 138 EDAC_CR243
AHB Bus Matrix244
- Figure 101 AHB Bus Matrix Masters and Slaves244
- Functional Description245
- How to Use AHB Bus Matrix267
- Register Map269
- Table 133 MM3_6_7_8_SECURITY269
- Table 147 AHB Bus Matrix Register Map269
High Performance DMA Controller270
- Figure 120 HPDMA Interfacing with MSSDDR Bridge and AHB Bus Matrix270
- Features271
- Figure 121 HPDMA Controller Block Diagram271
- Functional Description271
- How to Use HPDMA275
- HPDMA Controller Register Map280
- Hpdmad2Sar_Reg280
- Hpdmad3Sar_Reg280
- Table 149 HPDMA Register Map280
- SYSREG Control Register297
- Table 172 HPDMADR_REG297
- Table 173 SYSREG Control Registers297
Peripheral DMA298
- Features298
- Figure 129 PDMA Interfacing with AHB Bus Matrix298
- Functional Description299
- How to Use the PDMA305
- PDMA Register Map309
- SYSREG Control Registers317
- Table 189 SYSREG Control Registers317
Universal Serial Bus OTG Controller318
- Features318
- Functional Description319
- How to Use USB OTG Controller334
Ethernet MAC408
- Features408
- Figure 152 MSS Showing a TSEMAC408
- Functional Description409
  - EMAC Functional Blocks409
  - Figure 153 TSEMAC Block Diagram409
- TSEMAC PHY Interfaces411
- Table 320 MII Ports412
- Table 322 TBI Ports413
- Figure 154 RMII, RGMII, RTBI, Revmii, SMII Derived from Available Protocols by Appropriate Wrapper in Fabric414
- Figure 155 TBI Brought to Fabric for EPCS Soft IP for SGMII Interface414
- EMAC Operation415
  - Table 323 Tx/Rx Descriptor415
  - Table 324 Packetstartaddr415
  - Table 325 Packet Size415
  - Table 326 Next Descriptor416
  - Transmit Operation416
  - Receive Operation417
- How to Use TSEMAC418
  - Figure 156 External PHY Interface Selection in MSS EMAC Configurator418
  - Figure 157 Line Speed Selection in MSS EMAC Configurator419
  - Figure 158 External PHY Management Interface Selections in MSS EMAC Configurator420
  - Figure 159 MSS Ethernet Configurator with TBI Interface421
  - Figure 160 SGMII Interface Signals: TBI to SERDES421
  - SGMII Interface Configuration421
  - Figure 161 I/O Editor with SGMII and PHY Ports422
  - Figure 162 SECDED Configurator with Ethernet TX RAM and Ethernet RX RAM Configuration Options423
  - SECDED Features for TSEMAC Buffers423
  - Figure 163 Firmware Catalog Showing the Generation of Sample Project for TSEMAC424
  - Table 327 TSEMAC Firmware Drivers for Initialization and Configuration425
  - Table 328 TSEMAC Firmware Drivers for Ethernet PHY Management425
  - Table 329 TSEMAC Firmware Drivers for Transmit and Receive Operations425
- SYSREG Control Register for EMAC426
- Table 330 TSEMAC Firmware Drivers for Reading Status and Statistics426
- Table 331 MAC_CR Register in SYSREG Block426
- EMAC Configuration Register Summary427
- Table 332 EMAC M-AHB Register Map427
- Table 333 EMAC PE-MCXMAC Register Map427
- Dma_Irq427
- Mii_Command427
- Mii_Address427
- Mii_Ctrl427
- Table 334 EMAC A-MCXFIFO Register Map428
- Mii_Status428
- Station_Address1428
- Station_Address2428
- Fifo_Cfg1428
- Fifo_Cfg3428
- Fifo_Cfg4428
- Table 335 EMAC PE-MSTAT Transmit and Receive Counters Register Map429
- Table 336 EMAC PE-MSTAT Receive Counters Register Map429
- Tr1K429
- Trmax429
- Trmgv429
- Rbyt429
- Rpkt429
- Rfcs429
- Rbca429
- Rxcf429
- Table 337 EMAC PE-MSTAT Transmit Counters Register Map430
- Raln430
- Rflr430
- Rcde430
- Rcse430
- Rund430
- Rovr430
- Rfrg430
- Rjbr430
- Rdrp430
- Table 338 EMAC M-SGMII Register Map431
- EMAC Register Bit Definitions433
  - Table 342 DMA_RX_CTRL434
  - Table 347 CFG1435
  - Table 354 MII_COMMAND440
  - Table 355 MII_ADDRESS441
- Table 401 TBYT455
- Table 403 TMCA455
- Tscl456
- Tmcl456
- Tlcl456
- Txcl456
- Table 406 TDFR456
- Tncl457
- Tpfh457
- Tdrp457
- Tjbr457
- Tfcs457
- Table 417 TXCF457
- Table 412 TNCL457
- Tovr458
- Tund458
- Tfrg458
- Table 421 CAR1458
- Table 418 TOVR458
- Table 422 CAR2459
- Table 423 CAM1460
- Table 424 CAM2461
- Table 425 SGMII CONTROL463
- Table 426 SGMII STATUS463
- Table 427 an SGMII ADVERTISEMENT464
- An Link Partner Base465
- Table 429 an EXPANSION465
- An Next Page Transmit465
- Table 431 an NEXT466
- Table 432 EXTENDED STATUS466
- Table 433 JITTER DIAGNOSTICS467
- Table 434 TBI CONTROL467
- Coremacfilter Overview468
  - Features468
  - Figure 164 Coremacfilter Interaction with MSS MAC and GMII Ethernet PHY469
  - Figure 165 Coremacfilter Interaction with MSS MAC and SGMII Ethernet PHY469
CAN Controller470
- Features470
- Functional Description471
- CAN Controller Configuration476
- How to Use the MSS CAN Controller480
- Use Cases482
- CAN Controller Register Map485
MMUART Peripherals503
- Figure 178 MSS Showing MMUART Peripherals504
- Functional Description504
20 Watchdog Timer572
- Features572
- Figure 229 I 2 C Block Diagram573
- Functional Description573
  - Figure 230 8-Bit Data Transfer Cycle574
  - Port List574
  - Table 517 I 2 C Interface Signals574
  - Initialization575
  - Details of Operation576
- Figure 231 Pmbus and Smbus Devices Interface577
- Design Flow578
- Figure 233 MSS I2C Configurator579
- Figure 234 I 2 C Interface Signals579
- Figure 235 I 2 C Driver User's Guide580
- Table 519 MSS I 2 C Apis580
- Figure 236 I 2 C Sample Project581
- Figure 237 Interfacing External EEPROM to MSS I2C_0 - Block Diagram582
- Table 520 I 2 C Register Map584
- Table 521 Control Register (CTRL)585
- Table 522 Clock Rate (CR)585
- Table 524 Status Register - Master-Transmitter Mode586
- Table 525 STATUS Register - Master-Receiver Mode587
- Table 526 STATUS Register - Slave-Receiver Mode588
- Table 527 STATUS Register – Slave-Transmitter Mode590
- Data Register592
- Slave0 Address Register593
- Frequency Register594
- Glitch Register595
- Figure 239 GPIO Connected on APB Slave in MSS596
- Features596
- Figure 240 GPIO, IOMUX, and MSIO597
- MSS GPIO Functional Description597
  - Figure 241 MSS GPIO Block Diagram598
  - Figure 242 GPIO Configuration Register (GPIO_X_CFG)599
  - MSS GPIO Configuration Registers (GPIO_X_CFG)599
  - MSS GPIO Reset Functionality600
  - Figure 243 Enable GPIO in MSS Configurator602
- MSS GPIO Usage602
  - Figure 244 MSS GPIO Configurator603
  - Figure 245 Configuring GPIO Byte-Wise Reset604
  - Figure 246 Configuring Gpios as Input, Output, Tristate, or Bi-Directional605
  - Figure 247 Connectivity Preview606
  - Figure 248 GPIO Signals606
  - MSS GPIO Use Models607
  - Figure 249 GPIO Loopback Diagram608
- GPIO Register Map608
  - SYSREG Block Registers610
  - MSS GPIO Definitions611
  - GPIO System Reset Control Register612
  - Figure 250 Interfacing of COMM_BLK with AHB Bus Matrix627
- Functional Description627
  - Figure 251 Interfacing of COMM_BLK with System Controller628
  - Frame/Command Marker628
  - Clocks629
  - Figure 252 System Services Driver in Firmware Core Configurator630
  - Figure 253 System Services Driver Folder Hierarchy630
- How to Use the Communication Block630
  - Table 593 COMM_BLK Register Map631
  - Use Model631
  - Table 594 CONTROL632
- COMM_BLK Register Interface Details632
  - Interrupt Enable Register633
  - Word Data Register634
  - Figure 254 Microcontroller Subsystem Showing RTC635
- Features635
- Figure 255 RTC Block Diagram636
- Table 601 Calendar Counter Description636
- Functional Description636
  - Port List637
  - Table 602 RTC Interface Signals637
  - Details of Operation638
  - Design Flow639
  - Figure 256 Enabling RTC in the Libero SOC Design MSS Configurator639
  - Figure 257 RTC Configuration Window640
  - Figure 258 RTC Signals640
  - Figure 259 RTC Driver User Guide641
  - Table 603 RTC Apis641
  - Figure 260 RTC Examples642
  - RTC Use Model642
  - Counter Bit Positions643
  - Table 604 Allocation of Bits in Calendar Mode643
  - Table 605 Register Bit Allocation643
  - Table 606 Register Map for RTC643
  - Control Register644
  - Table 607 Control644
  - Mode Register645
  - Table 608 Mode645
  - Table 609 Prescaler645
  - Table 610 Alarm and Compare646
  - Table 611 Date and Time646
  - SYSREG Control Registers647
  - Table 612 the RTC_WAKEUP_CR in the SYSREG Block647
  - Features648
  - Figure 261 MSS Showing Timer Peripherals648
  - Figure 262 Timer Block Diagram649
  - Port List649
  - Table 613 Timer Interface Signals649
  - Table 614 Soft Reset Bit Definitions for System Peripheral649
  - Details of Operation650
  - Figure 263 Block Diagram 32-Bit Mode652
  - Figure 264 Block Diagram 64-Bit Mode652
  - Timxbgloadval652
  - Timxloadval652
  - Timx_Val652
  - Figure 265 Timer Driver User Guide653
  - Table 615 MSS Timer Apis653
- How to Use Timer653
  - Figure 266 Generating Sample Project655
  - Timer Use Models655
  - Table 616 Timer Register Map656
  - Tim64_Bgloadval_L656
  - Tim64_Bgloadval_U656
  - Tim64_Ris656
  - Tim64_Val_L656
  - Tim64_Val_U656
  - Tim64_Mis657
  - Tim64_Mode657
  - Timer X Value Register657
  - Timer X Raw Interrupt Status Register658
  - Timer X Masked Interrupt Status Register659
  - Timer 64 Load Value Lower Register660
  - Table 629 TIM64_CTRL661
  - Timer 64 Background Load Value Lower Register661
  - Timer 64 Raw Interrupt Status Register662
  - Features663
    - Figure 267 Microcontroller Subsystem Showing Watchdog Timer663
    - Figure 268 Block Diagram for the Watchdog Timer664
    - Functional Description664
    - Port List665
  - Table 633 Watchdog Timer Interface Signals665
  - Figure 269 Watchdog Timer Counter666
- How to Use the Watchdog Timer667
  - Design Flow668
  - Figure 270 Enabling Watchdog Timer in the Libero SOC Design MSS Configurator668
  - Figure 271 Watchdog Timer Configuration Window669
  - Figure 272 Watchdog Timer Signals669
  - Figure 273 RTC Driver User Guide670
  - Table 634 Watchdog Timer Apis670
  - Figure 274 Watchdog Timer Examples671
  - Watchdog Timer Use Models671
  - Table 635 Watchdog Timer Register Interface Summary672
  - Wdogload672
  - Wdogmvrp672
  - Wdogrefresh672
  - Wdogvalue672
  - Table 638 WDOGMVRP673
  - Table 640 WDOGENABLE673
  - Table 641 WDOGCONTROL674
  - Table 642 WDOGSTATUS674
  - Table 643 WDOGRIS674
  - Table 644 Watchdog Timer SYSREG675
- SYSREG Control Registers675
- Figure 275 Reset Signals Distribution in Smartfusion2 Devices676
- Reset Controller676
- Figure 276 Conceptual Block Diagram of Power-On Reset Generation677
- Functional Description677
- Figure 277 Power on Reset Delay Configuration678
- Figure 278 SYSRESET Macro678
- Figure 279 Power up to Functional Time Sequence Diagram679
- Power-Up to Functional Time Data680
- Figure 280 VDD Power-Up to Functional Time Design Setup681
- Figure 281 VDD Power-Up to Functional Timing Diagram682
- Table 645 VDD Power-Up to Functional Time682
- Figure 282 VDD Power-Up to Functional Time Flow684
- Figure 283 DEVRST_N Power-Up to Functional Timing685
- Table 646 DEVRST_N Power-Up to Functional Time685
- Figure 284 DEVRST_N Power-Up to Functional Time Flow687
- Figure 285 Functional Block Diagram of Reset Controller During Power-On Reset688
- Figure 286 SYSRESET_N Generation689
- Figure 287 Functional Block Diagram of Reset Controller During SYSRESET_N689
- Figure 288 Reset Controller with Only Block Level Resets690
- Figure 289 M3_SYS_RESET_N Generation691
- Figure 290 MDDR_AXI_RESET_N Generation691
- Figure 291 MDDR_APB_RESET_N Generation692
- Figure 292 WDOG_RESET_N Generation692
- Figure 293 FIC_2_APB_M_PRESET_N Generation693
- Table 647 GPIO_OUT Bank Reset Generation693
- Figure 294 MSS GPIO_OUT Reset Generation694
- Figure 295 Block Level Reset Generation694
- Coreresetp Soft Reset Controller694
  - Figure 296 MSS_READY Signal Generation695
  - Reset Topology695
  - Figure 297 Coreresetp Connectivity with Peripheral Resets696
  - Figure 298 Coreresetp Connectivity with SERDES_IF Block697
  - Implementation697
  - Figure 299 Timing for Reset Signals Initiated by the Assertion of POWER_N_RESET_N698
  - Figure 300 Timing for Reset Signals Initiated by the Assertion of FIC_2_APB_M_PRESET_N698
  - Timing Diagrams698
  - Figure 301 Timing for Reset Signals Initiated by the Assertion of EXT_RESET_IN_N699
  - Figure 302 Timing for Reset Signals Initiated by the Assertion of USER_FAB_RESET_IN_N699
  - Figure 303 Ramp Delay Configuration700
  - Figure 304 Configuring Reset700
- How to Use the Reset Controller700
  - Figure 305 Configuring Reset701
  - Figure 306 Connecting Fabric Logic701
  - Figure 307 Initialization Sub-System with Coreresetp Soft IP702
  - Figure 308 Initialization Sub-System for FIC Sub-Systems703
  - SYSREG Control Registers703
  - Table 648 Switch Register Map703
  - Figure 309 Register Write Protect704
  - SYSREG Block Register Write Protection704
  - Figure 310 Field Write Protect705
  - Figure 311 Bit Write Protect705
  - Table 649 Register Types705
  - Figure 312 RW-P Type706
  - Figure 313 RW Type707
  - Figure 314 RO Type707
  - Figure 315 RO-P Type708
  - Figure 316 RO-U Type708
  - Figure 317 Register Lock Bit Settings708
- Register Lock Bits Configuration708
- Figure 318 Lock Bit Configuration File709
- Table 650 SYSREG710
- Esram_Max_Lat710
- Envm_Remap_Base_Cr710
- Envm_Remap_Fab_Cr710
- Cc_Region_Cr710
- Cc_Lock_Base_Addr_Cr710
- Cc_Flush_Indx_Cr710
- Ddrb_Buf_Timer_Cr710
- Ddrb_Nb_Addr_Cr710
- Ddrb_Nb_Size_Cr710
- Master_Weight1_Cr711
- Soft_Irq_Cr711
- M3_Cr711
- Mddr_Cr711
- Wdog_Cr711
- Esram_Pipeline_Cr711
- Mss_Irq_Enable_Cr711
- Mac_Stat_Clronrd_Cr712
- Reset_Source_Cr712
- Cc_Dc_Err_Addr_Sr712
- Cc_Ic_Err_Addr_Sr712
- Cc_Sb_Err_Addr_Sr712
- Cc_Ic_Miss_Cntr_Sr712
- Cc_Ic_Hit_Cntr_Sr712
- Cc_Dc_Miss_Cntr_Sr712
- Cc_Dc_Hit_Cntr_Cr712
- Cc_Ic_Trans_Cntr_Sr712
- Ddrb_Hpd_Err_Adr_Sr713
- Ddrb_Dsbl_Dn_Sr713
- Esram0_Edac_Cnt713
- Esram1_Edac_Cnt713
- Mac_Edac_Tx_Cnt713
- Mac_Edac_Rx_Cnt713
- Usb_Edac_Cnt713
- Can_Edac_Cnt713
- Esram0_Edac_Adr713
- Esram1_Edac_Adr713
- M3_Sr714
- Etm_Count_Low714
- Etm_Count_High714
- Device_Sr714
- Device_Version714
- Mddr_Io_Calib_Status714
- Wdogload714
- Wdogmvrp714
- Fab_Prot_Size715
- Fab_Prot_Base715
- Mss_Gpio_Def715
- Mss_Internal_Sr715
- Wdogtimeoutevent715
- Clr_Mss_Counters715
- Mac_Stat_Clr_Cr715
- Iomuxcell_Config[N]715
- Table 651 Subset of System Registers716
- Register Details716
  - Esram Configuration Register717
  - Table 654 Esram Maximum Latency Values718
  - DDR Configuration Register718
  - Table 656 ENVM_CR719
  - Envm Remap Base Address Control Register720
  - Envm FPGA Fabric Remap Base Address Register721
  - Table 660 CC_CR722
  - Cache Region Control Register722
  - MSS DDR Bridge Buffer Timer Control Register723
  - MSS DDR Bridge Configuration Register724
  - Table 668 DDRB_CR725
  - EDAC Configuration Register725
  - Table 670 MASTER_WEIGHT0_CR726
  - Table 672 Programmable Weight Values726
  - Master Weight Configuration Register 1726
  - Software Interrupt Register727
  - Table 674 SOFT_RESET_CR728
  - M3 Configuration Register729
  - Table 676 FAB_IF_CR730
  - Loopback Control Register730
  - GPIO Input Source Select Control Register731
  - USB I/O Input Select Control Register732
  - Watchdog Configuration Register733
  - USB Configuration Register735
16 Mss Gpio597
21 Reset Controller627
18 RTC System635
24 Fabric Interface Controller636
22 System Register Block704
- RTC Wake up Configuration Register736
- MSS DDR PLL Status Low Configuration Register737
- MSS DDR PLL Status High Configuration Register738
- MSS DDR Fabric Alignment Clock Controller (FACC) Configuration Register 1739
- Table 695 Clock Ratio741
- MSS DDR Fabric Alignment Clock Controller Configuration Register 2741
- Table 696 MSSDDR_FACC2_CR742
- PLL LOCK Enable Control Register743
- MAC Status Clear on Read Control Register744
- Dcode Bus Error Address Status Register745
- Dcode Miss Control Status Register746
- MSS DDR Bridge DS Master Error Address Status Register747
- MSS DDR Bridge Buffer Empty Status Register748
- Esram0 EDAC Count749
- USB EDAC Count750
- MAC EDAC Receiver Address Register751
- Table 728 MM0_1_2_SECURITY752
- Table 729 MM4_5_DDR_FIC_SECURITY/MM4_5_FIC64_SECURITY752
- Security Configuration Register for Masters 0, 1, and 2752
- Table 730 MM3_6_7_8_SECURITY753
- Security Configuration Register for Masters 3, 6, 7, and 8753
- Security Configuration Register for Master 9754
- M3 Status Register755
- Device Status Register756
- Table 736 ENVM_PROTECT_USER757
- Smart Fusion2 Envm Status Register758
- Table 739 MSSDDR_PLL_STATUS759
- USB Status Register759
- DDRB Status Register760
- Table 747 USERCONFIG0761
- Table 748 USERCONFIG1761
- MSS DDR Clock Calibration Status761
  - Table 749 USERCONFIG2762
  - Table 750 USERCONFIG3762
  - Table 752 Region Size762
  - User Configuration Register 2762
  - Fabric Protected Base Address Register763
  - MSS GPIO Definitions764
  - MSS Internal Status Register765
  - Table 757 MSS_EXTERNAL_SR766
  - Watchdog Timeout Event767
  - Flush Configuration Register768
  - Table 760 CLR_EDAC_COUNTERS768
  - MAC Status Clear Control Register769
  - Table 761 FLUSH_CR769
  - Iomuxcell_Config[N] Configuration Register770
  - Table 764 MSS_IOMUXSEL5 [N][2:0]771
  - Table 765 MSS_IOMUXSEL4[N][2:0]771
  - Figure 319 the FIIC Connection to AHB Bus Matrix772
Fabric Interface Interrupt Controller772
- Figure 320 Block Diagram for Fabric Interface Interrupt Controller773

Microsemi SmartFusion2 - Figure 125 HPDMA Transfers Data between DDR Memory and MSS Internal Memory; Figure 126 HPDMA Transfers Data between SDR Memory and MSS Internal Memory

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