Microsemi SmartFusion2 - Coremacfilter Overview; Features

Ethernet MAC
UG0331 User Guide Revision 15.0 434
11.9 CoreMACFilter Overview
CoreMACFilter provides a solution for SmartFusion2 integrated media access control (MAC) address
filtering. The core provides an external filtering mechanism based on unicast (UCAD), multicast (MCAD),
and broadcast (BCAD) flags. It implements the desired mechanism to pass the frames to upper layer.
The upper layer determines to reject or accept the frames.
The CoreMACFilter filters the unwanted frames based on the following:
• Local base station MAC address
•MCAD
•BCAD
• Hash-unicast
• Hash-multicast of filter operating modes
A 128-bit hash table is used for hash-unicast and hash-multicast frame filtering. The frame filtering is
performed on the destination MAC address of the received frame. The CoreMACFilter has an APB
interface to allow the address filtering configurations and other MAC configurations.
11.9.1 Features
CoreMACFilter supports the following:
• Provides an advanced peripheral bus (APB) interface for control and status register access
• Supports UCAD, MCAD, and broadcast type of packets
• Supports hash based address filtering for UCAD and MCAD packets
• Provides mechanism to the upper layer to reject or accept the frames
8AUTO-
NEGOTIATION
SENSE
0x0 Set this bit to allow the auto-negotiation for 1000BASE-X, which is
used to exchange information between link partners.
Clear this bit when IEEE 802.3z Clause 37 behavior is desired,
which results in the link not coming up.
[7:6] Reserved 0x0 Reserved.
5 RECEIVE CLOCK
SELECT
0x0 Set this bit to configure the M-SGMII to accept a 125 MHz receive
clock from the SERDES PHY.
Clear this bit to allow the M-SGMII to accept dual split-phase 62.5
MHz receive clocks. This bit must be ‘0’ for correct M-SGMII
operation.
4 GMII MODE 0x0 When cleared, this bit defines the M-SGMII as being in
1000BASE-X SERDES mode. This bit must be ‘0’ for correct
M-SGMII operation.
[3:2] Reserved 0x0 Reserved
1 ENABLE WRAP 0x0 Set this bit to configure the SERDES in Loopback mode. Clear
this bit to permit normal operation.
0 ENABLE COMMA
DETECT
0x0 Set this bit to allow the SERDES PHY to perform code group
alignment based upon the detection of a comma.
Table 434 • TBI CONTROL (continued)