CAN Controller
UG0331 User Guide Revision 15.0 449
exclusive. Thus SRAM test mode can only be enabled when CAN controller is stopped and the CAN
controller can only be started when the SRAM test mode is stopped. In the SRAM test mode:
• Transparent read and write access to all SRAM memory locations is supported
• All message buffer write protect features are disabled
• Access to receive and transmit message buffer control registers is disabled
In SRAM test mode, the APB interface is used to access different SRAM address directly for test or
initialization purposes. At power-up, SRAM is not initialized and any READ action to the memory
locations would result in an ECC error if EDAC is enabled. Hence, putting the CAN controller into SRAM
test mode enables initialization of the SRAM so ECC errors at power-up do not occur if EDAC is enabled.
The following table provides address mapping between the APB and SRAM addresses.
Table 438 • APB to SRAM Address Mapping
APB Address SRAM Address Description
0x020 0x000 TxObject0:Control Bits
0x024 0x001 TxObject0:Identifier Bits
0x028 0x002 TxObject0:Data High Bits
0x02C 0x003 TxObject0:Data Low Bits
0x030-0x03C 0x004-0x007 TxObject1
0x040-0x04C 0x008-0x00B TxObject2
0x050-0x05C 0x00C-0x00F TxObject3
0x060-0x06C 0x010-0x013 TxObject4
0x070-0x07C 0x014-0x017 TxObject5
0x080-0x08C 0x018-0x01B TxObject6
0x090-0x09C 0x01C-0x01F TxObject7
0x0A0-0x0AC 0x020-0x023 TxObject8
0x0B0-0x0BC 0x024-0x027 TxObject9
0x0C0-0x0CC 0x028-0x02B TxObject10
0x0D0-0x0DC 0x02C-0x02F TxObject11
0x0E0-0x0EC 0x030-0x033 TxObject12
0x0F0-0x0FC 0x034-0x037 TxObject13
0x100-0x10C 0x038-0x03B TxObject14
0x110-0x11C 0x03C-0x03F TxObject15
0x120-0x12C 0x040-0x043 TxObject16
0x130-0x13C 0x044-0x047 TxObject17
0x140-0x14C 0x048-0x04B TxObject18
0x150-0x15C 0x04C-0x04F TxObject19
0x160-0x16C 0x050-0x053 TxObject20
0x170-0x17C 0x054-0x057 TxObject21
0x180-0x18C 0x058-0x05B TxObject22
0x190-0x19C 0x05C-0x05F TxObject23
0x1A0-0x1AC 0x060-0x063 TxObject24
0x1B0-0x1BC 0x064-0x067 TxObject25
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