Cache Controller
UG0331 User Guide Revision 15.0 138
4.2.3.1 Unimplemented Address Space
The cache matrix performs address decoding based on the memory map defined, and also to decide
which slave is addressed. Any access to RESERVED memory space in code region is considered
"unimplemented" from the point of view of the Cache Matrix.
4.2.3.2 Other Features of the Cache Matrix
• If any master attempts a write access to an unimplemented address space, the cache matrix
completes the handshake with the master, with HRESP error indication. No write occurs to any
slave.
• If any master attempts a read access from an unimplemented address space, the cache matrix
completes the handshake with the master, with HRESP error indication. Garbage data is returned in
this case.
• The cache matrix supports locked transactions from the SBUS towards the eSRAM AHB controller,
through the switch, by monitoring HMASTLOCK. The cache matrix initiates IDLE on the AHB bus
after every LOCKED transfer. SmartFusion2 SoC FPGA - Cache Controller Configuration
Application Note
• The cache matrix handshakes correctly with masters performing AHB-Lite bursts to any slave. The
ICache slave on the cache matrix supports bursts from the cache master.
NC NON
DDR
MS1 AHB Bus Matrix
Table 91 • Data Path for Various Maps (continued)
#
Memory Map
Mode Buses
Supported
Trans Region
Destination
Slave Routed Through
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