Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 348
10.3.10.9 EPx_TX_TYPE_REG Bit Definitions
10.3.10.10EPx_TX_INTERVAL_REG Bit Definitions
10.3.10.11EPx_RX_TYPE_REG Bit Definitions
Table 279 • EPx_TX_TYPE_REG
Bit
Number Name
Reset
Value Function
[7:6] EPx_Speed 0 Operating speed of the target device:
00: Unused
If selected, the target is assumed to be using the same connection
speed as the USB controller.
01: High
10: Full
11: Low
When the core is not configured with the multipoint option, these bits
should not be accessed.
[5:4] EPx_Protocol 0 The Cortex-M3 processor (or fabric master) should set this to select the
required protocol for the transmit endpoint:
00: Control
01: ISO
10: Bulk
11: Interrupt
[3:0] EPx_Target Endpoint
Number
0 The Cortex-M3 processor (or fabric master) should set this value to the
endpoint number contained in the transmit endpoint descriptor returned
to the USB controller during device enumeration.
Table 280 • EPx_TX_INTERVAL_REG
Bit
Number Name
Reset
Value Function
[7:0] EPx_Tx Polling Interval /
NAK Limit (m)
0 Defines the polling interval for endpointx transmit for interrupt and ISO
transfers. For bulk endpoints, this register sets the number of
frames/microframes after which the endpoint should timeout on
receiving a stream of NAK responses.
The value that is set defines number of frames/microframes (high speed
transfers), as given in Tab le 2 33, page 329.
Table 281 • EPx_RX_TYPE_REG
Bit
Number Name
Reset
Value Function
[7:6] EPx_Speed 0 Operating speed of the target device:
00: Unused (If selected, the target is assumed to be using the same
connection speed as the USB controller.)
01: High
10: Full
11: Low
When the core is not configured with the multipoint option, these bits
should not be accessed.
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