Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 81
3.6.8.2.1 Syntax
SBFX{cond} Rd, Rn, #lsb, #width
UBFX{cond} Rd, Rn, #lsb, #width
where:
cond is an optional condition code, see Conditional Execution, page 55.
Rd is the destination register.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield.
lsb
must be in the range 0 to 31.
width is the width of the bitfield and must be in the range 1 to 32-
lsb
.
3.6.8.2.2 Operation
SBFX
extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the destination
register.
UBFX
extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination
register.
3.6.8.2.3 Restrictions
Do not use SP and do not use PC
.
3.6.8.2.4 Condition Flags
These instructions do not affect the flags.
Examples
SBFX R0, R1, #20, #4 ; Extract bit 20 to bit 23 (4 bits) from R1 and sign
; extend to 32 bits and then write the result to R0.
UBFX R8, R11, #9, #10 ; Extract bit 9 to bit 18 (10 bits) from R11 and zero
; extend to 32 bits and then write the result to R8.
3.6.8.3 SXT and UXT
Sign extend and Zero extend.
3.6.8.3.1 Syntax
SXTextend{cond} {Rd,} Rm {, ROR #n}
UXTextend{cond} {Rd}, Rm {, ROR #n}
where:
• extend is one of:
•
B
: Extends an 8-bit value to a 32-bit value.
•
H
: Extends a 16-bit value to a 32-bit value.
• cond is an optional condition code, see Conditional Execution, page 55.
• Rd is the destination register.
• Rm is the register holding the value to extend.
•ROR #n is one of:
•
ROR #8:
Value from
Rm
is rotated right 8 bits.
•
ROR #16
: Value from
Rm
is rotated right 16 bits.
•
ROR #24
: Value from
Rm
is rotated right 24 bits.
•If
ROR #n
is omitted, no rotation is performed.
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