Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 86
3.6.9.3.4 Condition Flags
This instruction does not change the flags.
Example
ITTE NE ; Next 3 instructions are conditional
ANDNE R0, R0, R1 ; ANDNE does not update condition flags
ADDSNE R2, R2, #1 ; ADDSNE updates condition flags
MOVEQ R2, R3 ; Conditional move
CMP R0, #9 ; Convert R0 hex value (0 to 15) into ASCII
; ('0'-'9', 'A'-'F')
ITE GT ; Next 2 instructions are conditional
ADDGT R1, R0, #55 ; Convert 0xA -> 'A'
ADDLE R1, R0, #48 ; Convert 0x0 -> '0'
IT GT ; IT block with only one conditional instruction
ADDGT R1, R1, #1 ; Increment R1 conditionally
ITTEE EQ ; Next 4 instructions are conditional
MOVEQ R0, R1 ; Conditional move
ADDEQ R2, R2, #10 ; Conditional add
ANDNE R3, R3, #1 ; Conditional AND
BNE.W dloop ; Branch instruction can only be used in the last
; instruction of an IT block
IT NE ; Next instruction is conditional
ADD R0, R0, R1 ; Syntax error: no condition code used in IT block.
3.6.9.4 TBB and TBH
Table Branch Byte and Table Branch Halfword.
3.6.9.4.1 Syntax
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn is the register containing the address of the table of branch lengths. If
Rn
is PC, then the address of
the table is the address of the byte immediately following the
TBB
or
TBH
instruction.
Rm is the index register. This contains an index into the table. For halfword tables,
LSL #1
doubles the
value in
Rm
to form the right offset into the table.
3.6.9.4.2 Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets for
TBB
, or
halfword offsets for
TBH
.
Rn
provides a pointer to the table, and
Rm
supplies an index into the table. For
TBB
the branch offset is twice the unsigned value of the byte returned from the table. and for
TBH
the
branch offset is twice the unsigned value of the halfword returned from the table. The branch occurs to
the address at that offset from the address of the byte immediately after the
TBB
or
TBH
instruction.
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