Microsemi SmartFusion2 - Page 138

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 104
[28] PENDSVSET RW PendSV set-pending bit.
Write:
0: no effect
1: changes PendSV exception state to pending.
Read:
0: PendSV exception is not pending
1: PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV exception state to
pending.
[27] PENDSVCLR WO PendSV clear-pending bit.
Write:
0: no effect
1: removes the pending state from the PendSV exception.
[26] PENDSTSET RW SysTick exception set-pending bit.
Write:
0: no effect
1: changes SysTick exception state to pending.
Read:
0: SysTick exception is not pending
1: SysTick exception is pending.
[25] PENDSTCLR WO SysTick exception clear-pending bit.
Write:
0: no effect
1: removes the pending state from the SysTick exception.
This bit is WO. On a register read its value is Unknown.
[24] Reserved.
[23] Reserved for
Debug use
RO This bit is reserved for Debug use and reads-as-zero when the processor is not
in Debug.
[22] ISRPENDING RO Interrupt pending flag, excluding NMI and Faults:
0: interrupt not pending
1: interrupt pending.
[21:18] Reserved.
[17:12] VECTPENDIN
G
RO Indicates the exception number of the highest priority pending enabled
exception:
0: no pending exceptions
Nonzero: the exception number of the highest priority pending enabled
exception.
The value indicated by this field includes the effect of the BASEPRI and
FAULTMASK registers, but not any effect of the PRIMASK register.
[11] RETTOBASE RO Indicates whether there are preempted active exceptions:
0: there are preempted active exceptions to execute
1: there are no active exceptions, or the currently-executing exception is the
only active exception.
[10:9] Reserved.
[8:0] VECTACTIVE
a
RO Contains the active exception number:
0: Thread mode
Nonzero: The exception number
1
of the currently active exception.
Subtract 16 from this value to obtain the CMSIS IRQ number required to index
into the Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending, or
Priority Registers, see Ta bl e 11 , page 23.
Table 53 • ICSR Bit Assignments (continued)
Bits Name Type Function