Embedded NVM (eNVM) Controllers
UG0331 User Guide Revision 15.0 183
Note: Addresses that are not mentioned in the register range are either reserved or exclusively for System
Controller usage.
0x1FC REQACCESS 2:0 R/W 000 Any master on
AHB bus matrix.
This register can
only be accessed
using word, half
or byte accesses
to address
0×01FC.
Accesses to
addresses
0×1FD, 0×1FE,
and 0×1F should
not be used.
Request register access
When written with 0x01, it
will request exclusive
access.
Read indicates whether
access has granted or not
or which entity currently has
been granted access.
Read Value [2:0]
0XX: No entity has access
The XX value indicates who
had last access.
100: System controller
101: M3
110: Fabric
111: Other master (such as
PDMA or HDMA)
To release access rights,
write 0x00.
The System Controller may
gain immediate access by
writing 0x03 to this register.
When access is
relinquished, the WDBUFF
buffer, and RDBUFF buffers
are cleared.
Table 112 • Control Registers Description (continued)
OFFSET
HADDR[8:0] Register Name Width Type Default Access Rights Description
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