Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 299
• Initiating Remote Wake-Up: If the software wants to initiate a remote wake-up while the USB
controller is in Suspend mode, it should write a 1 to the LPMRES bit in LPM_CTRL_REG
(0x40043362)(Peripheral). This bit is self- clearing. Writing a 1 causes resume signaling to be driven
on the bus for 50 µs. The host responds by driving resume signaling for 60 µs to 990 µs. 10 µs after
the host stops driving resume, the USB controller transits to its normal operational state and is ready
for packet transmission. A resume interrupt is generated in LPM_INTR_REG
(0x40043364)(Peripheral Mode).
Suspend/Resume When Operating as a Host
• Entry into Suspend mode: When operating as a host, the controller initiates an LPM suspend
(transition from the L0 state to the L1 state) by initiating the following LPM transaction:
1. Software sets-up the desired attributes of the Suspend mode in LPM_ATTR_REG (0x40043360).
Enables remote wake-up and a large HIRD gives the peripheral more opportunity to conserve
power.
2. All LPM interrupts must be enabled in LPM_INTR_EN_REG (0x40043363).
3. Software should initiate the transaction by writing a 0x01 to LPM_CTRL_REG (0x40043362) (Host).
4. An interrupt is generated to inform software of the response to the LPM transaction. If an ACK is
received, the controller will be suspended automatically within 8 µs. This is the indication that the
controller is suspended.
5. If the response from the device has a bit stuff error or a PID error, an LPMERR interrupt
(LPM_INTR_REG (0x40043364) (Host Mode)) is generated. The hardware immediately attempts
the LPM transaction for two more times. The device is not suspended for 8 µs after the initial LPM,
so it will be able to respond to either of these subsequent LPM transactions. If an LPM timeout
occurs three times, the LPMNC and the LPMERR interrupts are set (LPM_INTR_REG). At this time,
software is unaware of the device state and must deduce it by other means.
• Sending Resume Signaling: Resume signaling should be generated by the software as follows:
1. All LPM interrupts should be enabled in LPM_INTR_EN_REG (0x40043363)
2. Software should write the LPMRES bit in LPM_CTRL_REG (0x40043362) (Host). This bit is self
clearing. This causes resume signaling to be generated on the bus for the time that is currently
specified in the HIRD field in LPM_ATTR_REG (0x40043360). Hardware assumes that this value
was used in the last LPM transaction that caused the suspend mode.
3. After HIRD + 10 µs, the controller transitions to its normal operational state and is ready for packet
transmission. A resume interrupt is generated in LPM_INTR_REG.
Note: Prior to resuming, the software must ensure that the system is completely restored from a low- power
state and that the inputs CLK and XCLK are available.
• Responding to Remote Wake-Up: If the remote wake-up feature is enabled in the LPM transaction
that caused the Suspend mode, the device may drive resume signaling on the bus. When this
occurs, the device drives the resume signaling bus for 50 µs. The controller immediately begins
driving resume signaling on the bus and will do so for 60 µs. 10 µs after completion of the resume
signaling, the controller transitions to its normal operating state and is ready for packet transmission.
At this time, the resume interrupt is generated in LPM_INTR_REG.
10.2.3.4 USB OTG Controller: Connect/Disconnect Operations
The particular behavior related to connecting and disconnecting the USB controller concerns its use in
Host mode or Peripheral mode in peer-to-peer communications.
10.2.3.4.1 Host Mode
Where the USB controller is operating in Host mode, the Cortex-M3 processor or fabric master starts the
session by setting the session bit of DEV_CTRL_REG (0x40043060). Power is then applied to VBus and
the core waits for a device to be connected.
When a device is detected, a connect interrupt is generated (the Conn bit in USB_IRQ_REG
(0x4004300A), goes high). The speed of the device that has been connected can be determined by
reading DEV_CTRL_REG (0x40043060), where the FSDev bit will be high for a high speed/full speed
device and the LSDev bit will be high for a low speed device. The Cortex-M3 processor or fabric master
should then reset the device. If both FSDev and HS Enab (POWER_REG (0x40043001)) are set, the
USB controller will try to negotiate for high speed operation. Whether this is successful, is indicated by
the HS mode bit (POWER_REG (0x40043001)).
The Cortex-M3 processor or fabric master should keep the Reset bit set for 20 ms to ensure that the
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