Ethernet MAC
UG0331 User Guide Revision 15.0 398
RESERVED 0x03 R/W 0x0 Reserved
AN SGMII
ADVERTISEMENT
0x04 R/W 0x0 This indicates that the link is up when the M-SGMII is
integrated into a PHY and is communicating with the
SGMII module in a MAC. It also indicates the link is
transferring data in Full-duplex mode and link speed.
The PHY address for the M-SGMII is 0x1E.
AN LINK PARTNER
BASE PAGE
ABILITY
0x05 RO - This indicates that the link is transferring data in
Full-duplex mode. This also indicates the speed of the
link.
The PHY address for the M-SGMII is 0x1E.
AN EXPANSION 0x06 RO 0x0 This indicates that the device supports the next page
function.
This also indicates that the new page is received and
stored in the applicable AN LINK PARTNER ABILITY or
AN NEXT PAGE register.
The PHY address for the M-SGMII is 0x1E.
AN NEXT PAGE
TRANSMIT
0x07 R/W 0x0 This indicates the additional next pages to follow and
message page.
Message pages are formatted pages, which carry a
predefined message code that is enumerated in IEEE
802.3u/Annex 28C.
The PHY address for the M-SGMII is 0x1E.
AN NEXT PAGE
TRANSMIT
0x08 RO - The link partner asserts this bit to indicate additional Next
Pages to follow.
This indicates the message page and the link partner’s
ability to comply with the message.
The PHY address for the M-SGMII is 0x1E.
EXTENDED
STATUS
0x0F RO 0xA000 This indicates that the PHY can be operated in
1000BASE-X FULL-DUPLEX, 1000BASE-X HALF-
DUPLEX, 1000BASE-T FULL-DUPLEX, 1000BASE-T
HALF-DUPLEX.
The PHY address for the M-SGMII is 0x1E.
JITTER
DIAGNOSTICS
0x10 R/W 0x0 This enables the M-SGMII to transmit the jitter test
patterns, which are defined in the IEEE 802.3z 36A.
This selects the jitter pattern that is to be transmitted in
diagnostics mode.
The PHY address for the M-SGMII is 0x1E.
TBI CONTROL 0x11 R/W 0x0 This allows the auto-negotiation function to sense either
a gigabit MAC in the auto-negotiation bypass mode or an
older gigabit MAC without the auto-negotiation capability.
This defines the M-SGMII as being in 1000BASE-X or
SERDES mode.
This allows the SERDES PHY to perform the code group
alignment based upon the detection of a comma.
The PHY address for the M-SGMII is 0x1E.
Table 338 • EMAC M-SGMII Register Map (continued)
Register name
Address
Offset
Register
Type Reset Value Description
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