Inter-Integrated Circuit Peripherals
UG0331 User Guide Revision 15.0 557
Notes:
• SLA = Slave address
• SLV = Slave
• REC = Receiver
• TRX = Transmitter
• SLA+W = Master sends slave address then writes data to slave
• SLA+R = Master sends slave address then reads data from slave
0xC0 Data byte is
transmitted; not
ACK (NACK) is
received.
No action 0 0 0 0 Switched to not-addressed SLV mode; no
recognition of own SLA or general call
address.
0 0 0 1 Switched to not-addressed SLV mode; own
SLA or general call address is recognized.
1 0 0 0 Switched to not-addressed SLV mode; no
recognition of own SLA or general call
address; START condition is transmitted
when the bus gets free.
1 0 0 1 Switched to not-addressed SLV mode; own
SLA or general call address is recognized;
START condition is transmitted when the bus
gets free.
0xC8 Last data byte is
transmitted; ACK is
received.
No action 0 0 0 0 Switched to not-addressed SLV mode; no
recognition of own SLA or general call
address.
0 0 0 1 Switched to not-addressed SLV mode; own
SLA or general call address is recognized.
1 0 0 0 Switched to not-addressed SLV mode; no
recognition of own SLA or general call
address; START condition is transmitted
when the bus gets free.
1 0 0 1 Switched to not-addressed SLV mode; own
SLA or general call address is recognized;
START condition is transmitted when the bus
gets free.
0xD8 25 ms SCL low
time is reached;
device must be
reset.
No action 0 Slave must proceed to reset state by clearing
the interrupt within 10 ms, according to
SMBus specification v2.0.
Table 527 • STATUS Register – Slave-Transmitter Mode (continued)
Status
Code Status
Data Register
Action
Control Register Bits
Next Action Taken by CoreSTA STO SI AA
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