MSS GPIO
UG0331 User Guide Revision 15.0 567
Following are the two reset resources of the MSS GPIO block:
• Hard reset:
• The MSS_GPIO_RESET_N is a reset signal generated from the FPGA fabric
• Power-on reset is a device reset signal
• Soft reset from the SYSREG block: There are two soft reset signals generated from the SYSREG
block: one for the output registers and another for the input and interrupt registers.
• The MSS_GPIO_SOFTRESET is a soft reset signal from the SYSREG block for the MSS GPIO
block input registers (GPIO_IN) and interrupt registers (GPIO_IRQ)
• There are four byte-wise soft reset signals from the SYSREG block to reset all the 32 GPIO
output registers. Each soft reset signal resets the GPIO output byte (8-GPIO_OUT registers).
Table 540, page 576 shows the soft reset signals from the SYSREG block
Each GPIO output byte reset is enabled by the control signals from the SYSREG block. The reset
enable feature for each GPIO output byte is used to hold the GPIO_OUT register values from not
getting affected by the reset source.
The GPIO output byte reset configuration in Libero SoC is explained in the Initializing the MSS GPIO,
page 570.
Note: If the byte reset enable signal (MSS_GPIO_X_Y_DEF) is enabled, the GPIO output byte
(GPIO_OUT[X:Y]) can be reset by the soft reset signal or hard reset signal, depending upon the Reset
select signal (MSS_GPIO_X_Y_SYSRESET_SEL).
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