Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 43
3.5.4.2 Fault Escalation and HardFaults
All faults exceptions except for HardFault have configurable exception priority, see System Handler
Priority Registers, page 110. Software can disable execution of the handlers for these faults, see System
Handler Control and State Register, page 112.
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another fault
handler. as described in Exception Model, page 37
In some situations, a fault with configurable priority is treated as a HardFault. This is called priority
escalation, and the fault is described as escalated to HardFault. Escalation to HardFault occurs when:
A fault handler causes the same kind of fault as the one it is servicing. This escalation to HardFault
occurs because a fault handler cannot preempt itself because it must have the same priority as the
current priority level.
A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because
the handler for the new fault cannot preempt the currently executing fault handler.
An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
A fault occurs and the handler for that fault is not enabled.
If a BusFault occurs during a stack push when entering a BusFault handler, the BusFault does not
escalate to a HardFault. This means that if a corrupted stack causes a fault, the fault handler executes
Bus error: BusFault
during exception
stacking
STKERR BusFault Status Register
during exception
unstacking
UNSTKERR
during instruction
prefetch
IBUSERR
Precise data bus error PRECISERR
Imprecise data bus
error
IMPRECISERR
Attempt to access a
coprocessor
UsageFault NOCP UsageFault Status Register
Undefined instruction UNDEFINSTR
Attempt to enter an
invalid instruction set
state
2
INVSTATE
Invalid
EXC_RETURN value
UsageFault INVPC UsageFault Status Register
Illegal unaligned load
or store
UNALIGNED
Divide By 0 DIVBYZERO
1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.
2. Attempting to use an instruction set other than the Thumb instruction set or returns to a non load/store-multiple instruction
with ICI continuation.
Table 24 • Faults (continued)
Fault Handler Bit name Fault status register
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