Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 66
must also have the same data size as the value loaded by the preceding Load-exclusive instruction. This
means software must always use a Load-exclusive instruction and a matching Store-Exclusive
instruction to perform a synchronization operation, see Synchronization Primitives, page 35.
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not
perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the
destination register, it is guaranteed that no other process in the system has accessed the memory
location between the Load-exclusive and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions between corresponding Load-Exclusive
and Store-Exclusive instruction to a minimum.
Note: The result of executing a Store-Exclusive instruction to an address that is different from that used in the
preceding Load-Exclusive instruction is unpredictable.
3.6.4.8.3 Restrictions
In these instructions:
• do not use PC
• do not use SP for
Rd
and
Rt
•for
STREX
,
Rd
must be different from both
Rt
and
Rn
• the value of
offset
must be a multiple of four in the range 0-1020.
3.6.4.8.4 Condition Flags
These instructions do not change the flags.
Examples
MOV R1, #0x1 ; Initialize the ‘lock taken’ value
try
LDREX R0, [LockAddr] ; Load the lock value
CMP R0, #0 ; Is the lock free?
ITT EQ ; IT instruction for STREXEQ and CMPEQ
STREXEQ R0, R1, [LockAddr] ; Try and claim the lock
CMPEQ R0, #0 ; Did this succeed?
BNE try ; No – try again
.... ; Yes – we have the lock.
3.6.4.9 CLREX
Clear Exclusive.
3.6.4.9.1 Syntax
CLREX{cond}
where:
cond is an optional condition code, see Conditional Execution, page 55.
3.6.4.9.2 Operation
Use
CLREX
to make the next
STREX
,
STREXB
, or
STREXH
instruction write 1 to its destination register and
fail to perform the store. It is useful in exception handler code to force the failure of the store exclusive if
the exception occurs between a load exclusive instruction and the matching store exclusive instruction in
a synchronization operation.
See Synchronization Primitives, page 35 for more information.
3.6.4.9.3 Condition Flags
These instructions do not change the flags.
To Next Page
Loading...
