Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 65
PUSH
uses the value in the SP register minus four as the highest memory address,
POP
uses the value in
the SP register as the lowest memory address, implementing a full-descending stack. On completion,
PUSH
updates the SP register to point to the location of the lowest stored value,
POP
updates the SP
register to point to the location immediately above the highest location loaded.
If a
POP
instruction includes PC in its reglist, a branch to this location is performed when the POP
instruction has completed. Bit[0] of the value read for the PC is used to update the APSR T-bit. This bit
must be 1 to ensure correct operation.
See LDM and STM, page 64 for more information.
3.6.4.7.3 Restrictions
In these instructions:
•
reglist
must not contain SP
•for the
PUSH
instruction,
reglist
must not contain PC
•for the
POP
instruction,
reglist
must not contain PC if it contains LR.
When PC is in
reglist
in a
POP
instruction:
• bit[0] of the value loaded for PC must be 1 for correct execution
• if the instruction is conditional, it must be the last instruction in the IT block.
3.6.4.7.4 Condition Flags
These instructions do not change the flags.
Examples
PUSH {R0,R4-R7} ; Push R0,R4,R5,R6,R7 onto the stack
PUSH {R2,LR} ; Push R2 and the link-register onto the stack
POP {R0,R6,PC} ; Pop r0,r6 and PC from the stack, then branch to the new PC
3.6.4.8 LDREX and STREX
Load and Store Register Exclusive.
3.6.4.8.1 Syntax
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
where:
cond is an optional condition code, see Conditional Execution, page 55.
Rd is the destination register for the returned status.
Rt is the register to load or store.
Rn is the register on which the memory address is based.
offset is an optional offset applied to the value in
Rn
. If
offset
is omitted, the address is the value in
Rn
.
3.6.4.8.2 Operation
LDREX
,
LDREXB
, and
LDREXH
load a word, byte, and halfword respectively from a memory address.
STREX
,
STREXB
, and
STREXH
attempt to store a word, byte, and halfword respectively to a memory
address. The address used in any Store-Exclusive instruction must be the same as the address in the
most recently executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction
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