Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 68
3.6.5.1 ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
3.6.5.1.1 Syntax
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only
where:
• op is one of:
•
ADD:
Add
•
ADC
: Add with Carry
•
SUB
: Subtract
•
SBC
: Subtract with Carry
•
RSB
: Reverse Subtract
• S is an optional suffix. If
S
is specified, the condition code flags are updated on the result of the
operation, see Conditional Execution, page 55.
• cond is an optional condition code, see Conditional Execution, page 55.
• Rd is the destination register. If
Rd
is omitted, the destination register is
Rn
.
• Rn is the register holding the first operand.
• Operand2 is a flexible second operand. See Flexible Second Operand, page 51 for details of the
options.
• imm12 is any value in the range 0-4095.
3.6.5.1.2 Operation
The
ADD
instruction adds the value of
Operand2
or
imm12
to the value in
Rn
.
The
ADC
instruction adds the values in
Rn
and
Operand2
, together with the carry flag.
The
SUB
instruction subtracts the value of
Operand2
or
imm12
from the value in
Rn
.
The
SBC
instruction subtracts the value of
Operand2
from the value in
Rn
. If the carry flag is clear, the
result is reduced by one.
The
RSB
instruction subtracts the value in
Rn
from the value of
Operand2
. This is useful because of the
wide range of options for
Operand2
.
Use
ADC
and
SBC
to synthesize multiword arithmetic, see Multiword Arithmetic Examples, page 70.
See also ADR, page 59.
Note:
ADDW
is equivalent to the
ADD
syntax that uses the
imm12
operand.
SUBW
is equivalent to the
SUB
syntax
that uses the
imm12
operand.
3.6.5.1.3 Restrictions
In these instructions:
•
Operand2
must not be SP and must not be PC
•
Rd
can be SP only in
ADD
and
SUB
, and only with the additional restrictions:
•
Rn
must also be SP
• any shift in
Operand2
must be limited to a maximum of 3 bits using
LSL
•
Rn
can be SP only in
ADD
and
SUB
•
Rd
can be PC only in the
ADD{cond} PC, PC, Rm
instruction where:
• you must not specify the S suffix
•
Rm
must not be PC and must not be SP
• if the instruction is conditional, it must be the last instruction in the IT block
• with the exception of the
ADD{cond} PC, PC, Rm
instruction,
Rn
can be PC only in
ADD
and
SUB
, and
only with the additional restrictions:
• you must not specify the S suffix
• the second operand must be a constant in the range 0 to 4095.
• When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to b00
before performing the calculation, making the base address for the calculation word-aligned.
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