Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 70
• Rd is the destination register.
• Rn is the register holding the first operand.
• Operand2 is a flexible second operand. See Flexible Second Operand, page 51 for details of the
options.
3.6.5.2.2 Operation
The
AND
,
EOR
, and
ORR
instructions perform bitwise AND, Exclusive OR, and OR operations on the
values in
Rn
and
Operand2
.
The
BIC
instruction performs an AND operation on the bits in
Rn
with the complements of the
corresponding bits in the value of
Operand2
.
The
ORN
instruction performs an OR operation on the bits in
Rn
with the complements of the
corresponding bits in the value of
Operand2
.
3.6.5.2.3 Restrictions
Do not use SP and do not use PC.
3.6.5.2.4 Condition Flags
If
S
is specified, these instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of
Operand2
, see Flexible Second Operand, page 51
• do not affect the V flag.
Examples
AND R9, R2, #0xFF00
ORREQ R2, R0, R5
ANDS R9, R8, #0x19
EORS R7, R11, #0x18181818
BIC R0, R1, #0xab
ORN R7, R11, R14, ROR #4
ORNS R7, R11, R14, ASR #32
3.6.5.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.
3.6.5.3.1 Syntax
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
• op is one of:
•
ASR
: Arithmetic Shift Right.
•
LSL
: Logical Shift Left.
•
LSR
: Logical Shift Right.
•
ROR
: Rotate Right.
• S is an optional suffix. If
S
is specified, the condition code flags are updated on the result of the
operation, see Conditional Execution, page 55.
• Rd is the destination register.
• Rm is the register holding the value to be shifted.
• Rs is the register holding the shift length to apply to the value in
Rm
. Only the least significant byte is
used and can be in the range 0 to 255.
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