Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 72
3.6.5.4.4 Condition Flags
This instruction does not change the flags.
Examples
CLZ R4,R9
CLZNE R2,R3
3.6.5.5 CMP and CMN
Compare and Compare Negative.
3.6.5.5.1 Syntax
CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
where:
cond is an optional condition code, see Conditional Execution, page 55.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See Flexible Second Operand, page 51 for details of the options.
3.6.5.5.2 Operation
These instructions compare the value in a register with
Operand2
. They update the condition flags on the
result, but do not write the result to a register.
The
CMP
instruction subtracts the value of
Operand2
from the value in
Rn
. This is the same as a
SUBS
instruction, except that the result is discarded.
The
CMN
instruction adds the value of
Operand2
to the value in
Rn
. This is the same as an
ADDS
instruction, except that the result is discarded.
3.6.5.5.3 Restrictions
In these instructions:
• do not use PC
•
Operand2
must not be SP.
3.6.5.5.4 Condition Flags
These instructions update the N, Z, C and V flags according to the result.
Examples
CMP R2, R9
CMN R0, #6400
CMPGT SP, R7, LSL #2
3.6.5.6 MOV and MVN
Move and Move NOT.
3.6.5.6.1 Syntax
MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2
where:
S is an optional suffix. If
S
is specified, the condition code flags are updated on the result of the operation,
see Conditional Execution, page 55.
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