Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 73
cond is an optional condition code, see Conditional Execution, page 55.
Rd is the destination register.
Operand2 is a flexible second operand. See Flexible Second Operand, page 51 for details of the options.
imm16 is any value in the range 0-65535.
3.6.5.6.2 Operation
The
MOV
instruction copies the value of
Operand2
into
Rd
.
When
Operand2
in a
MOV
instruction is a register with a shift other than
LSL #0
, the preferred syntax is the
corresponding shift instruction:
•
ASR{S}{cond} Rd, Rm, #n
is the preferred syntax for
MOV{S}{cond} Rd, Rm, ASR #n
•
LSL{S}{cond} Rd, Rm, #n
is the preferred syntax for
MOV{S}{cond} Rd, Rm, LSL #n
if
n
!= 0
•
LSR{S}{cond} Rd, Rm, #n
is the preferred syntax for
MOV{S}{cond} Rd, Rm, LSR #n
•
ROR{S}{cond} Rd, Rm, #n
is the preferred syntax for
MOV{S}{cond} Rd, Rm, ROR #n
•
RRX{S}{cond} Rd, Rm
is the preferred syntax for
MOV{S}{cond} Rd, Rm, RRX
.
Also, the
MOV
instruction permits additional forms of
Operand2
as synonyms for shift instructions:
•
MOV{S}{cond} Rd, Rm, ASR Rs
is a synonym for
ASR{S}{cond} Rd, Rm, Rs
•
MOV{S}{cond} Rd, Rm, LSL Rs
is a synonym for
LSL{S}{cond} Rd, Rm, Rs
•
MOV{S}{cond} Rd, Rm, LSR Rs
is a synonym for
LSR{S}{cond} Rd, Rm, Rs
•
MOV{S}{cond} Rd, Rm, ROR Rs
is a synonym for
ROR{S}{cond} Rd, Rm, Rs
See ASR, LSL, LSR, ROR, and RRX, page 71.
The
MVN
instruction takes the value of
Operand2
, performs a bitwise logical NOT operation on the value,
and places the result into
Rd
.
Note: The
MOVW
instruction provides the same function as
MOV
, but is restricted to using the
imm16
operand.
3.6.5.6.3 Restrictions
You can use SP and PC only in the
MOV
instruction, with the following restrictions:
• the second operand must be a register without shift
• you must not specify the
S
suffix.
When
Rd
is PC in a
MOV
instruction:
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
Note: Though it is possible to use
MOV
as a branch instruction, ARM strongly recommends the use of a
BX
or
BLX
instruction to branch for software portability to the ARM instruction set.
3.6.5.6.4 Condition Flags
•If
S
is specified, these instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of
Operand2
, see Flexible Second Operand, page 51
• do not affect the V flag.
Example
MOVS R11, #0x000B ; Write value of 0x000B to R11, flags get updated
MOV R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated
MOVS R10, R12 ; Write value in R12 to R10, flags get updated
MOV R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags.
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