UG0331 User Guide Revision 15.0 xvi
Figure 114 Use Case for eSRAM Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 115 Virtual eNVM View (After Chip Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 116 Virtual eNVM View for Soft Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 117 DDR Memory Remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 118 AHB Bus Matrix in Libero SoC Design MSS Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 119 AHB Bus Matrix Configuration Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 120 HPDMA Interfacing With MSSDDR Bridge and AHB Bus Matrix . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 121 HPDMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 122 HPDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 123 DMA Controller Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 124 Enable HPDMA in the Libero SOC Design MSS Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 125 HPDMA Transfers Data Between DDR Memory and MSS Internal Memory . . . . . . . . . . . . . . . . 243
Figure 126 HPDMA Transfers Data Between SDR Memory and MSS Internal Memory . . . . . . . . . . . . . . . . 243
Figure 127 HPDMA Driver User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 128 HPDMA Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 129 PDMA Interfacing with AHB Bus Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 130 PDMA Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 131 Flow of Ping-Pong Operation on DMA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 132 Enable PDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 133 PDMA AHB Bus Master Matrix Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 134 PDMA Transfers Data Between FIC and MSS Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 135 PDMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 136 PDMA Driver User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 137 PDMA Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 138 MSS Showing a USB OTG Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 139 USB OTG Controller in SmartFusion2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 140 Block Diagram for Connections between USB Controller and ULPI PHY through MSS . . . . . . . 288
Figure 141 Block Diagram for Connections Between USB Controller and UTMI PHY through FPGA Fabric 290
Figure 142 Basic USB Flow Diagram when USB Controller is in Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 143 Basic USB Flow Diagram when USB Controller is in USB Device/Peripheral Mode . . . . . . . . . . 293
Figure 144 Basic USB Flow Diagram when USB Controller is in OTG Mode . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 145 LPM State Transition Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 146 MSS Configurator with USB and GPIO Macros Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Figure 147 MSS USB Configurator with ULPI Interface Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 148 MSS USB Configurator with UTMI Interface Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 149 MSS GPIO Configurator with GPIO Settings for External USB PHY Reset . . . . . . . . . . . . . . . . . 303
Figure 150 I/O Editor Configurator with Settings for External USB PHY Reset Pin Mapping . . . . . . . . . . . . . 303
Figure 151 Firmware Catalog with MSS USB Firmware Drivers and Sample Class Drivers . . . . . . . . . . . . . 304
Figure 152 MSS Showing a TSEMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 153 TSEMAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Figure 154 RMII, RGMII, RTBI, RevMII, SMII Derived from Available Protocols by Appropriate Wrapper in Fabric
380
Figure 155 TBI Brought to Fabric for EPCS Soft IP for SGMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Figure 156 External PHY Interface Selection in MSS EMAC Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 157 Line Speed Selection in MSS EMAC Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Figure 158 External PHY Management Interface Selections in MSS EMAC Configurator . . . . . . . . . . . . . . . 386
Figure 159 MSS Ethernet Configurator with TBI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Figure 160 SGMII Interface Signals: TBI to SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Figure 161 I/O Editor With SGMII and PHY Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Figure 162 SECDED Configurator with Ethernet TX RAM and Ethernet RX RAM Configuration Options . . . 389
Figure 163 Firmware Catalog Showing the Generation of Sample Project for TSEMAC . . . . . . . . . . . . . . . . 390
Figure 164 CoreMACFilter Interaction with MSS MAC and GMII Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . 435
Figure 165 CoreMACFilter interaction with MSS MAC and SGMII Ethernet PHY . . . . . . . . . . . . . . . . . . . . . 435
Figure 166 CAN Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Figure 167 Transmit Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Figure 168 Receive Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Figure 169 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Figure 170 CAN Configurator GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Figure 171 Main Connection Options - Either MSIO or Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
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