Peripheral DMA
UG0331 User Guide Revision 15.0 276
CHANNEL_1_BUFFER_B_TRANSFER_COUNT 0x5C R/W 0 Channel 1 buffer B transfer
count
CHANNEL_2_CONTROL 0x60 R/W 0 Channel 2 Control register
CHANNEL_2_STATUS 0x64 R 0 Channel 2 Status register
CHANNEL_2_BUFFER_A_SRC_ADDR 0x68 R/W 0 Channel 2 buffer A source
address
CHANNEL_2_BUFFER_A_DST_ADDR 0x6C R/W 0 Channel 2 buffer A destination
address
CHANNEL_2_BUFFER_A_TRANSFER_COUNT 0x70 R/W 0 Channel 2 buffer A transfer
count
CHANNEL_2_BUFFER_B_SRC_ADDR 0x74 R/W 0 Channel 2 buffer B source
address
CHANNEL_2_BUFFER_B_DST_ADDR 0x78 R/W 0 Channel 2 buffer B destination
address
CHANNEL_2_BUFFER_B_TRANSFER_COUNT 0x7C R/W 0 Channel 2 buffer B transfer
count
CHANNEL_3_CONTROL 0x80 R/W 0 Channel 3 Control register
CHANNEL_3_STATUS 0x84 R 0 Channel 3 Status register
CHANNEL_3_BUFFER_A_SRC_ADDR 0x88 R/W 0 Channel 3 buffer A source
address
CHANNEL_3_BUFFER_A_DST_ADDR 0x8C R/W 0 Channel 3 buffer A destination
address
CHANNEL_3_BUFFER_A_TRANSFER_COUNT 0x90 R/W 0 Channel 3 buffer A transfer
count
CHANNEL_3_BUFFER_B_SRC_ADDR 0x94 R/W 0 Channel 3 buffer B source
address
CHANNEL_3_BUFFER_B_DST_ADDR 0x98 R/W 0 Channel 3 buffer B destination
address
CHANNEL_3_BUFFER_B_TRANSFER_COUNT 0x9C R/W 0 Channel 3 buffer B transfer
count
CHANNEL_4_CONTROL 0xA0 R/W 0 Channel 4 Control register
CHANNEL_4_STATUS 0xA4 R 0 Channel 4 Status register
CHANNEL_4_BUFFER_A_SRC_ADDR 0xA8 R/W 0 Channel 4 buffer A source
address
CHANNEL_4_BUFFER_A_DST_ADDR 0xAC R/W 0 Channel 4 buffer A destination
address
CHANNEL_4_BUFFER_A_TRANSFER_COUNT 0xB0 R/W 0 Channel 4 buffer A transfer
count
CHANNEL_4_BUFFER_B_SRC_ADDR 0xB4 R/W 0 Channel 4 buffer B source
address
CHANNEL_4_BUFFER_B_DST_ADDR 0xB8 R/W 0 Channel 4 buffer B destination
address
CHANNEL_4_BUFFER_B_TRANSFER_COUNT 0xBC R/W 0 Channel 4 buffer B transfer
count
Table 177 • SmartFusion2 SoC FPGA PDMA Register Map (continued)
Register Name
Address
Offset
Register
Type
Reset
Value Description
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