Memory-to-Memory DMA
2-48 ADSP-21368 SHARC Processor Hardware Reference
Memory-to-Memory DMA
Memory-to-memory (MTM) DMA allows programs to transfer blocks of
64-bit data from one internal memory location to another. This transfer
method uses two DMA channels, one for reading data and one for writing
data. This data transfer can be set up using the following procedure.
1. Program the DMA registers for both channels.
2. Set (=1) the MTMFLUSH bit in the MTMCTL register to flush the FIFO
and reset the read/write pointers.
3. Set (=1) the MTMEN bit in the MTMCTL register and clear (=0) the
MTMFLUSH bit.
A two-deep, 32-bit FIFO regulates the data transfer through the DMA
channels.
If the MTMI bit in the IMASK register is enabled, an interrupt occurs at the
end of each DMA (read/write). For more information, see “Interrupts” in
Appendix B, Interrupts.
Summary
Because the IOP registers are memory-mapped, the processors have access
to program DMA operations. A program sets up a DMA channel by writ-
ing the transfer’s parameters to the DMA parameter registers. After the
index, modify, and count registers (among others) are loaded with a start-
ing source or destination address, an address modifier, and a word count,
the processor is ready to start the DMA.
The SPI port, external port, serial ports, input data ports and the MTM
DMA engine each have a DMA enable bit (SPIDEN, DMAEN, SDEN
IDP_DMA_EN, or MTM_DEN) in their channel control register. Setting this bit
for a DMA channel with configured DMA parameters starts the DMA on
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