Clock Derivation
14-22 ADSP-21368 SHARC Processor Hardware Reference
Running Reset (ADSP-2137x)
All members of the SHARC processor family, including the ADSP-21375
and ADSP-21371, continue to support the hardware reset controlled with
the RESET pin. The de-assertion of this hardware reset enables the PLL and
asserting it resets the PLL. In the time it takes the PLL to acquire lock (set
to 4096 CLKIN cycles), the processor, internal memory, and the peripherals
are held in reset. Upon completion of the 4096 CLKIN cycles, the chip is
brought out of reset. This is indicated on the RESETOUT/CLKOUT pin for the
three valid boot modes (00, 01, 10 settings of BOOT_CFG1-0 pins). For
more information, see “Booting” on page 14-37.
In addition to the hardware reset, there is also support for a software reset,
which can be asserted by setting bit 0 of the SYSCTL register.
In the ADSP-21375 and ADSP-21371 processors, an additional feature,
called running reset, has been added. Running reset resets everything on
the chip, including the core and peripheral registers and the program
counter (PC). Running reset also clears all stacks and counters. However,
it does NOT reset the PLL (like the software reset) and the SDRAM con-
troller (to maintain SDRAM auto-refresh). De-assertion of this reset does
not result in a boot (unlike any of the other resets) even if a valid boot
mode is configured on the BOOT_CFG1-0 pins. Instead, the program
counter value is reset to the first location of internal memory (0x90005)
and the sequencer begins executing instructions starting from this address.
This feature has been added to allow the ADSP-2137x processors to exe-
cute self-modifying code that has previously overwritten existing code in
internal memory or as an external watchdog that activates in case there is a
malfunction or exception within a peripheral occurs, and a context reset of
the processor is sufficient to restore the state, (whereas a complete boot is
not required).
To Next Page
Loading...
Need help?
General
