ADSP-21368 SHARC Processor Hardware Reference 7-17
Input Data Port
A mechanism is provided to generate an interrupt when more than
a specified number of words are in the FIFO. This interrupt signals
the core to read the
IDP_FIFO register.
This method of moving data from the IDP FIFO is described in
the next section, “IDP Transfers Using the Core”.
• Eight dedicated DMA channels can sort and transfer the data into
one buffer per source channel. When the memory buffer is full, the
DMA channel raises an interrupt in the DAI interrupt controller.
This method of moving data from the IDP FIFO is described in
“IDP Transfers Using DMA” on page 7-20.
IDP Transfers Using the Core
The output of the FIFO can be directly fetched by reading from the
IDP_FIFO register. The IDP_FIFO register is used only to read and remove
the top sample from the FIFO, which is eight locations deep.
As data is read from the IDP_FIFO register, it is removed from the FIFO
and new data is copied into the register. The contents of the IDP_NSET bits
(bits 3–0 in the IDP_CTL0 register) represent a threshold number of entries
(N) in the FIFO. When the FIFO fills to a point where it has more than N
words (data in FIFO exceeds the value set in the IDP_NSET bit field), a DAI
interrupt is generated. This DAI interrupt corresponds to the
IDP_FIFO_GTN_INT bit, the eighth-level interrupt in the DAI_IRPTL_L or
DAI_IRPTL_H registers. The core uses this interrupt to detect when data
needs to be read.
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