ADSP-21368 SHARC Processor Hardware Reference 5-15
Serial Ports
The endian format (LSB versus MSB first) is selectable by the
LSBF bit of
the SPCTL register (see “Endian Format” on page 5-45 for more details).
Data packing of two serial words into a 32-bit word is also selectable. The
PACK bit in the SPCTL register controls this option. See “Data Packing and
Unpacking” on page 5-45 for more details.
Data Transfers
Serial port data is transferred using two different methods:
• DMA transfers
• Core-driven single word transfers
DMA transfers can be set up to transfer a configurable number of serial
words between the SPORT buffers (TXSPxA, TXSPxB, RXSPxA, and RXSPxB)
and internal memory automatically. For more information on Sport DMA
operations, see DMA Block transfers section on “DMA Block Transfers”
on page 5-73. Core-driven transfers use SPORT interrupts to signal the
processor core to perform single word transfers to/from the SPORT buff-
ers (TXSPxA, TXSPxB, RXSPxA, and RXSPxB). See “SPORT Interrupts” on
page 5-72 for more details.
Status Information
Serial ports provide status information about data buffers through the
DXS_A and DXS_B status bits and error status through the ROVF or TUVF bits
in the SPCTLx register. See “Serial Port Control Registers (SPCTLx)” on
page 5-59 for more details.
Depending on the
SPTRAN setting, these bits reflect the status of either the
TXSPxy or RXSPxy data buffers.
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