ADSP-21368 SHARC Processor Hardware Reference 9-17
S/PDIF Transmitter/Receiver
The receiver also detects errors in the S/PDIF stream. These error bits are
stored in the status register, which can be read by the core. Optionally, an
interrupt may be generated to notify the core on error conditions. The
extracted serial data is transmitted on the data pin in I
2
S format. The
extracted clock, frame sync, and data are routed through SRU1.
The S/PDIF receiver receives any S/PDIF stream with a sampling fre-
quency range of 32 kHz – 15% to 192 kHz + 15% range.
The serial output from the receiver is 24-bit I
2
S serial data which con-
forms to the format shown in Figure 9-5 on page 9-14.
S/PDIF Receiver Registers
The S/PDIF receiver uses the registers described in the following sections.
More detail can be found in “Sony/Philips Digital Interface Registers” on
page A-86.
DIRCTL is the receiver control register. It is a 32-bit, read/write register
located at address 0x24A8 and is used to enable the receiver, control mute,
PLL and SCDF mode. This register is described in detail in “Receiver
Control Register (DIRCTL)” on page A-92.
DIRSTAT is the receiver status register. It is a 32-bit, read-only register
that is used to store the error bits. The error bits are sticky on read. Once
they are set, they remain set until the register is read. This register also
contains the lower byte of the 40-bit channel status information.
DIRCHANL, DIRCHANR are the channel status for the subframes regis-
ters. They provide status information for subframe A (left channel) bytes
1, 2, 3, and 4 and subframe B (right channel) bytes 1, 2, 3, and 4. These
32-bit, read/write registers are located at address 0x24AA and 0x24AB.
See also “Left Channel Status for Subframe A Registers (DITCHANAx)”
on page A-89 and “Right Channel Status for Subframe B Registers (DIT-
CHANBx)” on page A-90.
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