ADSP-21368 SHARC Processor Hardware Reference 14-53
System Design
Execution Stalls
The following events can cause an execution stall for the
ADSP-21367/8/9 and ADSP-2137x SHARC processors:
• One cycle on a program memory data access with instruction cache
miss
• Two cycles on non-delayed branches
• Two cycles on normal interrupts
• One to two cycles on short loops with small iterations
• On an IDLE instruction, execution is halted while waiting for an
external event, such as an interrupt
• In a sequence of three instructions of the types shown below, the
processor may stall for one cycle:
Instruction 1: Compute instruction affecting flags such as
R2 = R3 - R4;
Instruction 2: Conditional instruction involving post-modify
addressing such as IF EQ DM(I1,M1) = R15;
Table 14-15. Latencies and Throughput
Operation Minimum Data
Delay (cycles)
Maximum Throughput
(cycles/ transfer)
Interrupts (IRQ2-0) 3 -
DMA chain initialization 7–11 -
Serial ports
1
35 32
1 Processor-to -processor transfers using 32-bit words.
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